Abstract: An apparatus for controlling an output voltage of a switching mode power supply (SMPS) by adjusting a switching duty ratio is provided. A comparator outputs a state signal varying depending on a comparison result between an output voltage of the SMPS and a reference voltage. A clock generator generates an internal chip operating frequency and a switching frequency of the SMPS. A digital controller determines on/off of current cells depending on the state signal input from the comparator. A digital pulse width modulator (DPWM) determines a duty ratio of a digital pulse width modulation signal by determining a charging/discharging time of an internal capacitor based on an amount of current of the current cell.

Abstract: A current detection device for a multi-sensor array is provided. The current detection device includes a current input unit, a current conversion unit, a digital conversion unit, and a voltage applying unit. The current input unit amplifies a plurality of current signals input from a multi-sensor array according to a predetermined current minor ratio, and fixes each of node voltages to which the plurality of current signals are input. The current conversion unit converts each of the amplified current signals into an amplified voltage signal using a plurality of feedback resistors and an operational amplifier which are connected in parallel. The digital conversion unit converts each of the amplified voltage signals converted by the current conversion unit into a digital value. The voltage applying unit generates voltages for driving each of the multi-sensor array, the current input unit, the current conversion unit, and the digital conversion unit, and applies the generated voltages thereto.

Abstract: An apparatus for controlling an output voltage of a switching mode power supply (SMPS) by adjusting a switching duty ratio is provided. A comparator outputs a state signal varying depending on a comparison result between an output voltage of the SMPS and a reference voltage. A clock generator generates an internal chip operating frequency and a switching frequency of the SMPS. A digital controller determines on/off of current cells depending on the state signal input from the comparator. A digital pulse width modulator (DPWM) determines a duty ratio of a digital pulse width modulation signal by determining a charging/discharging time of an internal capacitor based on an amount of current of the current cell.

Abstract: Disclosed are a method and an apparatus of near field scan calibration, and more particularly, a method and an apparatus for near field scan calibration for calibrating a characteristic of an antenna for near field scan measurement of a semiconductor chip. The apparatus for near field scan calibration includes: a plane-type text fixture having a plane shape; an antenna positioned spaced apart from the plane-type test fixture by a set spacing distance and acquiring data including a magnetic field; and a spectrum analyzer analyzing the data acquired by the antenna.

Abstract: Disclosed are a method and an apparatus of near field scan calibration, and more particularly, a method and an apparatus for near field scan calibration for calibrating a characteristic of an antenna for near field scan measurement of a semiconductor chip. The apparatus for near field scan calibration includes: a plane-type text fixture having a plane shape; an antenna positioned spaced apart from the plane-type test fixture by a set spacing distance and acquiring data including a magnetic field; and a spectrum analyzer analyzing the data acquired by the antenna.

Abstract: A clock synchronization device is disclosed that includes a phase detecting unit for detecting a phase difference between an external clock signal and an internal clock signal, a binary code generating unit for outputting a binary code value according to output signals from the phase detecting unit, a code converting unit for converting the binary code value from the binary code generating unit into a thermometer code value, a D/A converting unit for outputting a voltage corresponding to the thermometer code value from the code converting unit and a clock synchronization control unit for outputting the internal clock signal from the external clock signal according to the output voltage from the D/A converting unit. As the result, the clock synchronization device is controlled by employing the D/A converting unit for converting the binary code to the thermometer code in order to decrease the number of the registers, the leakage current and the chip size.

Abstract: A synchronous semiconductor device having a delay locked loop capable of adjusting phase offset between an external clock signal and an internal clock signal after a packaging process is completed is disclosed. The disclosed synchronous semiconductor device may include a replica delay for replicating delay time of an internal circuit and a delay controller for controlling the replicated delay time.

Abstract: A clock synchronization device is disclosed that includes a phase detecting unit for detecting a phase difference between an external clock signal and an internal clock signal, a binary code generating unit for outputting a binary code value according to output signals from the phase detecting unit, a code converting unit for converting the binary code value from the binary code generating unit into a thermometer code value, a D/A converting unit for outputting a voltage corresponding to the thermometer code value from the code converting unit and a clock synchronization control unit for outputting the internal clock signal from the external clock signal according to the output voltage from the D/A converting unit. As the result, the clock synchronization device is controlled by employing the D/A converting unit for converting the binary code to the thermometer code in order to decrease the number of the registers, the leakage current and the chip size.

Abstract: A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.

Abstract: A repair circuit substitutes a defective cell with a redundancy cell. For the purpose, the repair circuit includes an antifuse programmed by a voltage difference of both ends thereof, a programming circuit for programming the antifuse, a detection circuit for detecting whether the antifuse is programmed or unprogrammed by using a first and a second power stabilization signal of a power up reset circuit, wherein the detection is performed during a power stabilization period or after the power stabilization period, a latch circuit for latching the result of the detection to thereby generate an output signal, and a redundancy circuit having a redundancy cell for repairing the defective cell in response to the output signal of the latch circuit.

Abstract: A synchronous semiconductor device having a delay locked loop capable of adjusting phase offset between an external clock signal and an internal clock signal after a packaging process is completed is disclosed. The disclosed synchronous semiconductor device may include a replica delay for replicating delay time of an internal circuit and a delay controller for controlling the replicated delay time.

Abstract: An antifuse repair circuit is disclosed for selectively programming a specific antifuse to replace a defective cell with a redundant cell.

Abstract: An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation.

Abstract: A repair circuit substitutes a defective cell with a redundancy cell. For the purpose, the repair circuit includes an antifuse programmed by a voltage difference of both ends thereof, a programming circuit for programming the antifuse, a detection circuit for detecting whether the antifuse is programmed or unprogrammed by using a first and a second power stabilization signal of a power up reset circuit, wherein the detection is performed during a power stabilization period or after the power stabilization period, a latch circuit for latching the result of the detection to thereby generate an output signal, and a redundancy circuit having a redundancy cell for repairing the defective cell in response to the output signal of the latch circuit.

Abstract: An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation.

Abstract: A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.

Abstract: An antifuse repair circuit is disclosed for selectively programming a specific antifuse to replace a defective cell with a redundant cell.

Abstract: The anti-fuse circuit includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses; a programming voltage generator consisting of an oscillator and a charge pump; and an anti-fuse unit circuits for the program/read of anti-fuse states. For an anti-fuse program at the special test mode, a program address generation circuit having inputs of control signals and addresses activates the programming voltage generator and makes a special or program address for selection of anti-fuse. In the normal mode, the program address generation circuit and an internal power generator remain at an inactive state. In anti-fuse unit circuit, the program address and the programming voltage signal from the programming voltage generator serve to switch the terminal of the anti-fuse up to a programming voltage level when the anti-fuse is selected for programming of anti-fuse elements.