Patents by Inventor Jae-Man Yoon

Jae-Man Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210294113
    Abstract: A camera module includes: a housing; a lens module disposed in the housing; a driving assembly configured to move the lens module in a direction of an optical axis or a direction intersecting the optical axis; and a reinforcing structure formed integrally with the housing, and electrically connected to the driving assembly.
    Type: Application
    Filed: October 9, 2020
    Publication date: September 23, 2021
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Man PARK, Bong Won JEONG, Young Bok YOON, Jung Seok LEE, Soo Cheol LIM
  • Patent number: 10923390
    Abstract: A method for fabricating a semiconductor device includes: forming a plurality of bit line structures over a semiconductor substrate; forming a line-type opening between the bit line structures; forming a sacrificial spacer on both sidewalls of the line-type opening; forming a line-type plug filling the line-type opening over the sacrificial spacer; forming a plurality of plug isolation openings that expose the sacrificial spacer by etching a portion of the line-type plug in a direction crossing the bit line structures; forming a plurality of air gaps by removing the exposed sacrificial spacer; removing a remaining line-type plug below the plug isolation openings to form a plurality of island-type plugs; and forming a plug isolation layer inside the plug isolation openings to isolate neighboring island-type plugs from each other.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae-Man Yoon
  • Publication number: 20200203213
    Abstract: A method for fabricating a semiconductor device includes: forming a plurality of bit line structures over a semiconductor substrate; forming a line-type opening between the bit line structures; forming a sacrificial spacer on both sidewalls of the line-type opening; forming a line-type plug filling the line-type opening over the sacrificial spacer; forming a plurality of plug isolation openings that expose the sacrificial spacer by etching a portion of the line-type plug in a direction crossing the bit line structures; forming a plurality of air gaps by removing the exposed sacrificial spacer; removing a remaining line-type plug below the plug isolation openings to form a plurality of island-type plugs; and forming a plug isolation layer inside the plug isolation openings to isolate neighboring island-type plugs from each other.
    Type: Application
    Filed: March 3, 2020
    Publication date: June 25, 2020
    Inventor: Jae-Man YOON
  • Patent number: 10622249
    Abstract: A method for fabricating a semiconductor device includes: forming a plurality of bit line structures over a semiconductor substrate; forming a line-type opening between the bit line structures; forming a sacrificial spacer on both sidewalls of the line-type opening; forming a line-type plug filling the line-type opening over the sacrificial spacer; forming a plurality of plug isolation openings that expose the sacrificial spacer by etching a portion of the line-type plug in a direction crossing the bit line structures; forming a plurality of air gaps by removing the exposed sacrificial spacer; removing a remaining line-type plug below the plug isolation openings to form a plurality of island-type plugs; and forming a plug isolation layer inside the plug isolation openings to isolate neighboring island-type plugs from each other.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae-Man Yoon
  • Publication number: 20190103302
    Abstract: A method for fabricating a semiconductor device includes: forming a plurality of bit line structures over a semiconductor substrate; forming a line-type opening between the bit line structures; forming a sacrificial spacer on both sidewalls of the line-type opening; forming a line-type plug filling the line-type opening over the sacrificial spacer; forming a plurality of plug isolation openings that expose the sacrificial spacer by etching a portion of the line-type plug in a direction crossing the bit line structures; forming a plurality of air gaps by removing the exposed sacrificial spacer; removing a remaining line-type plug below the plug isolation openings to form a plurality of island-type plugs; and forming a plug isolation layer inside the plug isolation openings to isolate neighboring island-type plugs from each other.
    Type: Application
    Filed: May 25, 2018
    Publication date: April 4, 2019
    Inventor: Jae-Man YOON
  • Patent number: 9576965
    Abstract: A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 21, 2017
    Assignee: SK HYNIX INC.
    Inventors: Jae Man Yoon, Young Bog Kim, Yun Seok Chun, Woong Choi, Woo Jun Lee
  • Publication number: 20150380415
    Abstract: A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 31, 2015
    Inventors: Jae Man YOON, Young Bog KIM, Yun Seok CHUN, Woong CHOI, Woo Jun LEE
  • Publication number: 20150115392
    Abstract: A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.
    Type: Application
    Filed: March 28, 2014
    Publication date: April 30, 2015
    Applicant: SK HYNIX INC.
    Inventors: Jae Man YOON, Young Bog KIM, Yun Seok CHUN, Woong CHOI, Woo Jun LEE
  • Patent number: 8958257
    Abstract: A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier that is disposed above or below the memory cell array to be overlapped with the memory cell array in a planar fashion, connected to at least one bit line connected to the at least one cell bit line, and at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell; a decompression unit for decompressing a signal having a lower voltage level from among a signal of the at least one bit line and a signal of the at least one complementary bit line; a boosting unit for boosting a signal having a higher voltage level from among the signal of the at least one bit line and the signal of the at least one complementary bit line; and an equalizing unit for eq
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: February 17, 2015
    Inventor: Jae Man Yoon
  • Patent number: 8791526
    Abstract: A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-man Yoon, Hyeong-sun Hong, Kwang-youl Chun, Makoto Yoshida, Deok-sung Hwang, Chul Lee
  • Patent number: 8623724
    Abstract: A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-Jung Kim, Yong-Chul Oh, Jae-Man Yoon, Hyun-Woo Chung, Hyun-Gi Kim, Kang-Uk Kim
  • Patent number: 8557664
    Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-sik Cho, Kwang-youl Chun, Jae-man Yoon, Bong-soo Kim
  • Patent number: 8502341
    Abstract: Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Lee, Hyeong-Sun Hong, Deok-Sung Hwang, Jae-Man Yoon, Bong-Soo Kim
  • Patent number: 8482045
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20130107652
    Abstract: A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier that is disposed above or below the memory cell array to be overlapped with the memory cell array in a planar fashion, connected to at least one bit line connected to the at least one cell bit line, and at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell; a decompression unit for decompressing a signal having a lower voltage level from among a signal of the at least one bit line and a signal of the at least one complementary bit line; a boosting unit for boosting a signal having a higher voltage level from among the signal of the at least one bit line and the signal of the at least one complementary bit line; and an equalizing unit for eq
    Type: Application
    Filed: January 7, 2011
    Publication date: May 2, 2013
    Inventor: Jae Man Yoon
  • Patent number: 8409953
    Abstract: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: April 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Man Yoon, Yong-Chul Oh, Hui-Jung Kim, Hyun-Woo Chung, Hyun-Gi Kim, Kang-Uk Kim
  • Patent number: 8373214
    Abstract: A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: February 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Man Yoon, Hui-Jung Kim, Hyun-Woo Chung, Hyun-Gi Kim, Kang-Uk Kim, Yong-Chul Oh
  • Patent number: 8343831
    Abstract: In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Uk Kim, Jae-Man Yoon, Yong-Chul Oh, Hui-Jung Kim, Hyun-Woo Chung, Hyun-Gi Kim
  • Publication number: 20120273898
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 1, 2012
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20120276698
    Abstract: A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 1, 2012
    Inventors: Hui-Jung KIM, Yong-Chul Oh, Jae-Man Yoon, Hyun-Woo Chung, Hyun-Gi Kim, Kang-Uk Kim