Patents by Inventor Jae-Man Youn

Jae-Man Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7317230
    Abstract: A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: January 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Ho Lee, Dong-Gun Park, Jae-Man Youn, Chul Lee
  • Patent number: 7279774
    Abstract: A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: October 9, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Woun-Suck Yang, Du-Heon Song, Jae-Man Youn
  • Publication number: 20050184348
    Abstract: A MOS transistor includes a gate structure extending forrom a semiconductor substrate in a vertical direction is disclosed. The gate structure includes a gate electrode extending from the substrate in a vertical direction, and a gate insulation layer enclosing the gate electrode. A channel pattern encloses the gate insulation layer, and a first conductive pattern extends from a lower portion of the channel pattern in a first direction verticalperpendicular to the channel pattern and in parallel with the substrate. A second conductive pattern extends from an upper portion of the channel pattern in a second direction verticalperpendicular to the channel pattern and in parallel with the substrate. Accordingly, the channel length of the MOS transistor is determined by a distance between the first and second conductive patterns, and a channel width of the MOS transistor is determined by a diameter of the gate structure. Short channel and narrow width effects are sufficiently prevented in a MOS transistor.
    Type: Application
    Filed: February 15, 2005
    Publication date: August 25, 2005
    Inventors: Jae-Man Youn, Dong-Gun Park, Choong-Ho Lee, Makoto Yoshida, Chul Lee
  • Publication number: 20050173768
    Abstract: A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.
    Type: Application
    Filed: January 21, 2005
    Publication date: August 11, 2005
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Choong-Ho Lee, Dong-Gun Park, Jae-Man Youn, Chul Lee
  • Publication number: 20050056888
    Abstract: Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.
    Type: Application
    Filed: August 11, 2004
    Publication date: March 17, 2005
    Inventors: Jae-Man Youn, Dong-gun Park, Gyo-young Jin, Yoshida Makoto, Tai-su Park