Patents by Inventor Jae Moo CHOI
Jae Moo CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092141Abstract: An air conditioning device for a vehicle includes: a housing having an inside divided into an inflow space, a heat exchange space, and an outflow space, which are straightly arranged, and having a plurality of discharge ports, which communicates with an interior, at the inflow space; a blowing unit disposed at the inflow space of the housing and configured to blow air; a heat exchange unit disposed at the heat exchange space of the housing and configured to adjust a temperature of conditioned air by exchanging heat with air; and an opening-closing door disposed at the outflow space of the housing and configured to open and close the plurality of discharge ports such that conditioned air at an adjusted temperature selectively flows to the plurality of discharge ports. The air conditioning device adjusts the temperature of conditioned air for respective modes and reduces a flow resistance of air.Type: ApplicationFiled: March 8, 2023Publication date: March 21, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, DOOWON CLIMATE CONTROL CO., LTD.Inventors: Kwang Ok Han, Young Tae Song, Yong Chul Kim, Gee Young Shin, Su Yeon Kang, Jae Sik Choi, Dae Hee Lee, Byeong Moo Jang, Ung Hwi Kim, Jae Won Cha, Won Jun Joung, Byung Guk An
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Publication number: 20240085469Abstract: A transmitting and receiving circuit may include a first CMOS inverter configured to receive a first power supply signal and a first input signal. The transmitting and receiving circuit may include a first calculation amplifier including a non-inverted input terminal connected to an output terminal of the first CMOS inverter, and a first resistor connected between the output terminal of the first calculation amplifier and a first node. The output terminal of the first calculation amplifier and an inverted input terminal of the first calculation amplifier may be connected to each other. A first output signal may have a level smaller than that of the first input signal and may be output to the first node.Type: ApplicationFiled: September 11, 2023Publication date: March 14, 2024Inventors: Seong Kwan LEE, Min Ho KANG, Hyung-Sun RYU, Cheol Min PARK, Jun Yeon WON, Jae Moo CHOI
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Publication number: 20240088177Abstract: An image sensing device is provided to include a pixel array having a plurality of pixels arranged in a matrix shape. Each of the pixels includes: a control node configured to generate a hole current in a substrate; a detection node configured to capture photocharge migrated by the hole current, formed in a shape whose at least part is partially open, and disposed to surround the control node, and a low resistance region including a dielectric layer formed in the substrate, and disposed in the opening on of the detection node. The low resistance region includes an inner low resistance region disposed between the control node and the center of the pixel.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Hyung June YOON, Jong Eun KIM, Jong Chae KIM, Jae Won LEE, Jae Hyung JANG, Hoon Moo CHOI
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Patent number: 10962581Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.Type: GrantFiled: September 19, 2019Date of Patent: March 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Nyeong Yun, Jae Moo Choi, Jong Pill Park, Jae Hong Kim
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Publication number: 20200011915Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Inventors: JI NYEONG YUN, JAE MOO CHOI, JONG PILL PARK, JAE HONG KIM
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Patent number: 10444270Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.Type: GrantFiled: March 10, 2017Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Nyeong Yun, Jae Moo Choi, Jong Pill Park, Jae Hong Kim
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Publication number: 20170261548Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.Type: ApplicationFiled: March 10, 2017Publication date: September 14, 2017Inventors: JI NYEONG YUN, JAE MOO CHOI, JONG PILL PARK, JAE HONG KIM
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Patent number: 9293226Abstract: A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.Type: GrantFiled: July 28, 2014Date of Patent: March 22, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Hyun Baek, Jae Moo Choi, Jae Hee Han, In Su Yang, Hyun Soo Jung
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Publication number: 20150100838Abstract: A memory test device for testing a memory device is provided. The memory test device includes a sequencer configured to output first and second sequencer outputs that are different from each other in response to a sequencer input. A first pattern generator is configured to output a first test pattern according to the first sequencer output. A second pattern generator is configured to output a second test pattern according to the second sequencer output. A selector is coupled to the first and second pattern generators and configured to output write data according to the first test pattern and the second test pattern.Type: ApplicationFiled: July 28, 2014Publication date: April 9, 2015Inventors: Jae Hyun BAEK, Jae Moo CHOI, Jae Hee HAN, In Su YANG, Hyun Soo JUNG