Patents by Inventor Jae-Myung Choe

Jae-Myung Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240037307
    Abstract: Systems and methods for simulating a semiconductor device, a method among includes; generating meshes associated with a simulated semiconductor device using a semiconductor device simulator, extracting nodes from information associated with the meshes, extracting edges connected between the nodes using information associated with the meshes, generating graph information in relation to the nodes and edges, applying the graph information to a graph neural network (GNN) learning model, and predicting change in the meshes in response to change in state information applied to the simulated semiconductor device using the GNN learning model.
    Type: Application
    Filed: January 19, 2023
    Publication date: February 1, 2024
    Inventors: WON IK JANG, SANG HOON MYUNG, JAE MYUNG CHOE
  • Patent number: 11263368
    Abstract: A computing system includes memory configured to store instructions and a nozzle library, and a processor configured to access the memory and to execute the instructions. The instructions cause the computing system to select at least one nozzle unit as a selected at least one nozzle unit based on the nozzle library and to place the selected at least one nozzle unit at corresponding location coordinates, to create multiple volume meshes for the process chamber, and to simulate the flow of the gas through the selected at least one nozzle unit in the process chamber based on the multiple volume meshes in the process chamber. The nozzle library includes information about multiple nozzle units of which each has multiple volume meshes formed therein. The nozzle units have different shapes from each other.
    Type: Grant
    Filed: June 3, 2018
    Date of Patent: March 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yub Ie, Jung-Geun Jee, Jae-Myung Choe
  • Patent number: 11182518
    Abstract: An apparatus for generating 3D shape data of a showerhead includes: a data processor that generates data sets comprising information indicating values of a first distance between an upper surface of a wafer and a showerhead, information indicating positions on the wafer and information about a fluid flow physical quantity value and determines a function representing a relationship among the various information; an input unit that receives condition data comprising a target fluid flow physical quantity value for each of the positions; and a database that stores information about the function. The data processor obtains information about a second distance, which has the target fluid flow physical quantity value, between the upper surface of the wafer and the showerhead at each of the positions, extracts spatial coordinate information of a lower surface of the showerhead, and generates 3D shape data of the showerhead using the spatial coordinate information.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 23, 2021
    Inventors: Sang Yub Ie, Jung Geun Jee, Sung Youn Chung, Jae Myung Choe
  • Patent number: 10790168
    Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Bo Shim, Hyuk Kim, Sun Taek Lim, Jae Myung Choe, Jeon Il Lee, Sung-Il Cho
  • Publication number: 20190228120
    Abstract: An apparatus for generating 3D shape data of a showerhead includes: a data processor that generates data sets comprising information indicating values of a first distance between an upper surface of a wafer and a showerhead, information indicating positions on the wafer and information about a fluid flow physical quantity value and determines a function representing a relationship among the various information; an input unit that receives condition data comprising a target fluid flow physical quantity value for each of the positions; and a database that stores information about the function. The data processor obtains information about a second distance, which has the target fluid flow physical quantity value, between the upper surface of the wafer and the showerhead at each of the positions, extracts spatial coordinate information of a lower surface of the showerhead, and generates 3D shape data of the showerhead using the spatial coordinate information.
    Type: Application
    Filed: September 11, 2018
    Publication date: July 25, 2019
    Inventors: Sang Yub Ie, Jung Geun Jee, Sung Youn Chung, Jae Myung Choe
  • Publication number: 20190122903
    Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.
    Type: Application
    Filed: May 7, 2018
    Publication date: April 25, 2019
    Inventors: SEUNG BO SHIM, HYUK KIM, SUN TAEK LIM, JAE MYUNG CHOE, JEON IL LEE, SUNG-IL CHO
  • Publication number: 20190080033
    Abstract: A computing system includes memory configured to store instructions and a nozzle library, and a processor configured to access the memory and to execute the instructions. The instructions cause the computing system to select at least one nozzle unit as a selected at least one nozzle unit based on the nozzle library and to place the selected at least one nozzle unit at corresponding location coordinates, to create multiple volume meshes for the process chamber, and to simulate the flow of the gas through the selected at least one nozzle unit in the process chamber based on the multiple volume meshes in the process chamber. The nozzle library includes information about multiple nozzle units of which each has multiple volume meshes formed therein. The nozzle units have different shapes from each other.
    Type: Application
    Filed: June 3, 2018
    Publication date: March 14, 2019
    Inventors: Sang-Yub IE, Jung-Geun JEE, Jae-Myung CHOE
  • Patent number: 10128112
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cho Eun Lee, Jin Bum Kim, Kang Hun Moon, Jae Myung Choe, Sun Jung Kim, Dong Suk Shin, Il Gyou Shin, Jeong Ho Yoo
  • Publication number: 20180096845
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.
    Type: Application
    Filed: May 16, 2017
    Publication date: April 5, 2018
    Inventors: Cho Eun LEE, Jin Bum KIM, Kang Hun MOON, Jae Myung CHOE, Sun Jung KIM, Dong Suk SHIN, IL GYOU SHIN, Jeong Ho YOO
  • Publication number: 20170051409
    Abstract: A thin film deposition apparatus, including a processing chamber; a boat in the processing chamber, the boat to accommodate a plurality of substrates therein; and a nozzle to supply a source gas to the processing chamber to form a thin film on each of the substrates, the nozzle including a plurality of T-shaped nozzle pipes, each of the T-shaped nozzle pipes including a first pipe having closed ends and a second pipe coupled to a middle portion of the first pipe.
    Type: Application
    Filed: May 26, 2016
    Publication date: February 23, 2017
    Inventors: Young Jin NOH, Dong Min SON, Jae Myung CHOE, Jae Young AHN, Cheol Kyu YANG
  • Publication number: 20170022610
    Abstract: A wafer processing apparatus may include a reaction tube extending in a vertical direction and defining a process chamber for receiving a boat that holds a plurality of wafers. A gas injector may be configured to supply a reaction gas into the process chamber and may include a gas distributor extending in the vertical direction in the reaction tube. The gas injector may have a plurality of ejection holes for spraying the reaction gas. An inner diameter of the gas distributor may be at least 10 mm, and a sectional area ratio of the total sectional area of the ejection holes to a sectional area of the gas distributor is about 0.3 or less.
    Type: Application
    Filed: March 10, 2016
    Publication date: January 26, 2017
    Inventors: Eun-Sung Seo, Yong-Kwon Kim, Young-Jin Noh, Young-Chang Song, Jae-Myung Choe, Ji-Hoon Choi, Sang-Cheol HA