Patents by Inventor Jae O. Choo

Jae O. Choo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect formation with chamferless via, and related interconnect
    Patent number: 10566231
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Martin J. O'Toole, Christopher J. Penny, Jae O. Choo, Adam L. da Silva, Craig Child, Terry A. Spooner, Hsueh-Chung Chen, Brendan O'Brien, Keith P. Donegan
  • INTERCONNECT FORMATION WITH CHAMFERLESS VIA, AND RELATED INTERCONNECT
    Publication number: 20190333805
    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Martin J. O'Toole, Christopher J. Penny, Jae O. Choo, Adam L. da Silva, Craig Child, Terry A. Spooner, Hsueh-Chung Chen, Brendan O'Brien, Keith P. Donegan