Patents by Inventor Jae Phil SHIM

Jae Phil SHIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10644155
    Abstract: Disclosed is a semiconductor device, which includes: forming a first channel layer including a Group III-V compound or germanium (Ge) and having a first semiconductor characteristics on a first substrate; forming a second channel layer including a Group III-V compound or germanium (Ge) and having a second semiconductor characteristics different from the first semiconductor characteristics on the first channel layer; forming a bonding layer containing an oxide on a second channel layer; allowing the bonding layer to be bound to the second substrate so that a structure including the bonding layer, the second channel layer, the first channel layer and the first substrate may be stacked on the second substrate; removing the first substrate stacked on the second substrate; and removing the first channel layer from a partial region of the structure stacked on the second substrate.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 5, 2020
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyung-jun Kim, Sanghyeon Kim, Jae-Phil Shim
  • Patent number: 10504771
    Abstract: A method for manufacturing a semiconductor device includes: forming a sacrificial layer on a first substrate, the sacrificial layer being made of a material whose lattice constant is different from that of germanium (Ge) by a preset threshold or below; forming a germanium (Ge) layer on the sacrificial layer; forming an insulation layer on a second substrate; bonding the germanium (Ge) layer onto the insulation layer; and removing the sacrificial layer and the first substrate by etching the sacrificial layer in a state where the germanium (Ge) layer is bonded to the insulation layer. In this method, a germanium-on-insulator (GeOI) structure having various surface orientations may be formed by means of epitaxial lift-off (ELO), and a strain may be applied to the germanium (Ge) layer using a lattice constant of the sacrificial layer.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 10, 2019
    Assignee: Korea Institute of Science and Technology
    Inventors: Hyung-Jun Kim, Sanghyeon Kim, Jae-Phil Shim, Yeon-Su Kim, Heejeong Lim
  • Publication number: 20180350988
    Abstract: Disclosed is a semiconductor device, which includes: forming a first channel layer including a Group III-V compound or germanium (Ge) and having a first semiconductor characteristics on a first substrate; forming a second channel layer including a Group III-V compound or germanium (Ge) and having a second semiconductor characteristics different from the first semiconductor characteristics on the first channel layer; forming a bonding layer containing an oxide on a second channel layer; allowing the bonding layer to be bound to the second substrate so that a structure including the bonding layer, the second channel layer, the first channel layer and the first substrate may be stacked on the second substrate; removing the first substrate stacked on the second substrate; and removing the first channel layer from a partial region of the structure stacked on the second substrate.
    Type: Application
    Filed: April 18, 2018
    Publication date: December 6, 2018
    Inventors: Hyung-jun KIM, Sanghyeon KIM, Jae-Phil SHIM
  • Patent number: 9941168
    Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 10, 2018
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sanghyeon Kim, Hyung-jun Kim, Jae-Phil Shim, Seong Kwang Kim, Won Jun Choi
  • Publication number: 20180082900
    Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.
    Type: Application
    Filed: June 23, 2017
    Publication date: March 22, 2018
    Inventors: Sanghyeon KIM, Hyung-jun KIM, Jae-Phil SHIM, Seong Kwang KIM, Won Jun CHOI
  • Publication number: 20180076084
    Abstract: A method for manufacturing a semiconductor device includes: forming a sacrificial layer on a first substrate, the sacrificial layer being made of a material whose lattice constant is different from that of germanium (Ge) by a preset threshold or below; forming a germanium (Ge) layer on the sacrificial layer; forming an insulation layer on a second substrate; bonding the germanium (Ge) layer onto the insulation layer; and removing the sacrificial layer and the first substrate by etching the sacrificial layer in a state where the germanium (Ge) layer is bonded to the insulation layer. In this method, a germanium-on-insulator (GeOI) structure having various surface orientations may be formed by means of epitaxial lift-off (ELO), and a strain may be applied to the germanium (Ge) layer using a lattice constant of the sacrificial layer.
    Type: Application
    Filed: January 26, 2017
    Publication date: March 15, 2018
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyung-Jun KIM, Sanghyeon KIM, Jae-Phil SHIM, Yeon-Su KIM, Heejeong LIM
  • Patent number: 8779411
    Abstract: The present disclosure provides a light emitting diode and a method of manufacturing the same. The light emitting diode includes a graphene layer on a second conductive semiconductor layer and a plurality of metal nanoparticles formed on some region of the graphene layer, whereby adhesion between the second conductive semiconductor layer comprised of an inorganic material and the graphene layer is enhanced, thereby securing stability and reliability of the light emitting diode. In addition, the light emitting diode allows uniform spreading of electric current, thereby allowing stable emission of light through a surface area of the light emitting diode.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: July 15, 2014
    Assignee: Gwanju Institute of Science and Technology
    Inventors: Dong Seon Lee, Jae Phil Shim, Seong Ju Park, Min Hyeok Choe, Do Hyung Kim, Tak Hee Lee
  • Publication number: 20130285012
    Abstract: The present disclosure provides a light emitting diode and a method of manufacturing the same. The light emitting diode includes a graphene layer on a second conductive semiconductor layer and a plurality of metal nanoparticles formed on some region of the graphene layer, whereby adhesion between the second conductive semiconductor layer comprised of an inorganic material and the graphene layer is enhanced, thereby securing stability and reliability of the light emitting diode. In addition, the light emitting diode allows uniform spreading of electric current, thereby allowing stable emission of light through a surface area of the light emitting diode.
    Type: Application
    Filed: November 16, 2012
    Publication date: October 31, 2013
    Applicant: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Dong Seon LEE, Jae Phil SHIM, Seong Ju PARK, Min Hyeok CHOE, Do Hyung KIM, Tak Hee LEE