Patents by Inventor Jae Pil Yang

Jae Pil Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BATTERY INSULATION SHEET, MANUFACTURING METHOD THEREOF, AND BATTERY MODULE COMPRISING THE BATTERY INSULATION SHEET
    Publication number: 20250062516
    Abstract: Example embodiments include a battery insulation sheet having a structure in which a first substrate, an aerogel layer, and a second substrate are laminated, wherein opposite surfaces of the aerogel layer is in contact with the first substrate or the second substrate adjacent thereto. Example embodiments also include a method of manufacturing a battery insulation sheet, and a battery module including the battery insulation sheet.
    Type: Application
    Filed: May 28, 2024
    Publication date: February 20, 2025
    Applicants: SAMSUNG SDI CO., LTD., DAEHYUP TECH CO., LTD.
    Inventors: Myung Heui WOO, Ha Na RA, Hye Jin PARK, Seung Yong YANG, Jae Hyun LEE, Bo Kyung RYU, Sang Hoon KIM, Jong Pil HWANG, Hyung Sek CHOI, Ho Joon KIM
  • Method of packaging a microchip having a footprint that is larger than that of the integrated circuit
    Patent number: 7749810
    Abstract: A method of packaging an integrated circuit singulates a wafer to form an integrated circuit, positions the integrated circuit on a carrier, and passivates the integrated circuit after the positioning the integrated circuit on the carrier. At this point, the integrated circuit is secured to the carrier. The method also electrically connects the integrated circuit to a plurality of exposed conductors.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: July 6, 2010
    Assignee: Analog Devices, Inc.
    Inventor: Jae Pil Yang
  • Method of Packaging a Microchip
    Publication number: 20080303151
    Abstract: A method of packaging an integrated circuit singulates a wafer to form an integrated circuit, positions the integrated circuit on a carrier, and passivates the integrated circuit after the positioning the integrated circuit on the carrier. At this point, the integrated circuit is secured to the carrier. The method also electrically connects the integrated circuit to a plurality of exposed conductors.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Applicant: ANALOG DEVICES, INC.
    Inventor: Jae Pil Yang