Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy ve

Abstract: An integrated circuit device includes a substrate, a peripheral circuit structure disposed on the substrate, the peripheral circuit structure including a peripheral circuit and a lower wiring connected to the peripheral circuit, a conductive plate covering a portion of the peripheral circuit structure, a cell array structure disposed on the peripheral circuit structure with the conductive plate therebetween, the cell array structure including a memory cell array and an insulation layer surrounding the memory cell array, a through hole via passing through the insulation layer in a direction vertical to a top surface of the substrate to be connected to the lower wiring, and an etch guide member disposed in the insulation layer at the same level as the conductive plate to contact a portion of the through hole via.

Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy ve

Abstract: A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.

Abstract: Disclosed are 3D semiconductor memory device, electronic systems including the same, and methods of fabricating the same. The 3D semiconductor memory device includes lower selection lines extending in a first direction on a substrate and spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction, a middle stack structure including electrode layers and electrode interlayer dielectric layers that are alternately stacked on the lower selection lines, upper selection lines extending in the first direction on the middle stack structure and spaced apart from each other in the second direction, a first polishing stop layer disposed between the middle stack structure and the lower selection lines. The first polishing stop layer includes a material different from that of the electrode interlayer dielectric layers.

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structur

Abstract: A semiconductor device and a data storage system, the device including a lower structure; and an upper structure on the lower structure and including a memory cell array, wherein the lower structure includes a semiconductor substrate, first and second active regions spaced apart from each other in a first direction on the semiconductor substrate, the first and second active regions being defined by an isolation insulating layer on the semiconductor substrate, and first and second gate pattern structures extending in the first direction to cross the first and second active regions, respectively, on the semiconductor substrate, the first gate pattern structure and the second gate pattern structure have first and second end portions spaced apart from each other in a facing manner in the first direction, respectively, and the first and second end portions are concavely curved in opposite directions away from each other in a plan view.

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure with peripheral transistors on the first substrate, a second substrate on the peripheral circuit structure, a lower insulating layer in contact with a side surface of the second substrate, a top surface of the lower insulating layer having a concave profile, a first stack on the second substrate, the first stack including repeatedly alternating first interlayer dielectric layers and gate electrodes, and a first mold structure on the lower insulating layer, the first mold structure including repeatedly alternating sacrificial layers and second interlayer dielectric layers, and a top surface of the first mold structure being at a level lower than a topmost surface of the first stack.

Abstract: A semiconductor device includes a stack structure and an insulation structure that covers the stack structure, a vertical memory structure that penetrates the stack structure, and a separation structure that penetrates the stack structure and has an upper surface located at a higher level than an upper surface of the vertical memory structure. The stack structure includes three gate stack groups stacked in a vertical direction. Each of the three gate stack groups includes gate layers stacked and spaced apart from each other in the vertical direction. At a height level between a lowermost gate layer and an uppermost gate layer, a side surface of the vertical memory structure includes memory side surface slope changing portions, and a side surface of the separation structure includes separation side surface slope changing portions positioned at substantially a same height level as some of the memory side surface slope changing portions.

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

Abstract: A semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. Memory structures are disposed on the horizontal patterns. The memory structures include source structures and electrode structures. A division structure is disposed between adjacent horizontal patterns in the first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a level lower than a level of the source structures. The etch stop pattern is connected to a lower portion of the division structure.

Abstract: A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate, electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

Abstract: An integrated circuit device includes a substrate, a peripheral circuit structure disposed on the substrate, the peripheral circuit structure including a peripheral circuit and a lower wiring connected to the peripheral circuit, a conductive plate covering a portion of the peripheral circuit structure, a cell array structure disposed on the peripheral circuit structure with the conductive plate therebetween, the cell array structure including a memory cell array and an insulation layer surrounding the memory cell array, a through hole via passing through the insulation layer in a direction vertical to a top surface of the substrate to be connected to the lower wiring, and an etch guide member disposed in the insulation layer at the same level as the conductive plate to contact a portion of the through hole via.

Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy ve

Abstract: A three-dimensional (3D) semiconductor memory device including; first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structur

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structur