Abstract: One aspect of the present invention provides work shoes each including an outsole, a midsole, an inner board, and a mid-insole from the ground up, wherein a thickness of the mid-insole is twice or more a thickness of the midsole, the mid-insole includes a substrate including a plurality of first sensors, an electronic module, and a wiring configured to connect the first sensors and the electronic module, and a body part in which a groove, into which the electronic module downwardly protruding from the substrate is inserted, is formed, the electronic module includes a communication module and a battery, the communication module communicates with an external device, and the external device analyzes information received from work shoes and then notifies a worker and a manager of the information.

Abstract: The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.

Abstract: Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.

Abstract: The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.

Abstract: Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.

Abstract: An apparatus for suspending power of a processing system having a plurality of core blocks connected in series includes a system controller which receives input data and determines whether to suspend a supply of power to the processing system based on the input data. A converter converts a format of the input data, and a determining unit determines whether the converted input data is valid data. Valid data is data which will be processed by the plurality of core blocks. A series of controllers in the apparatus shift output from the determining unit through the series of controllers. Each controller temporarily stores the output from the determining unit prior to shifting the output from the determining unit to a next controller in the series of controllers. Also, each controller is associated with one of the plurality of core blocks, and controls a supply of power to the associated core block based on output from the system controller and the output from the determining unit temporarily stored therein.