Abstract: A method for fabricating a semiconductor memory device including a matrix of memory cells each constituted by one transistor and one capacitor and capable of obtaining a large capacitance for achieving a high integration and yet maintaining superior characteristics of its elements. The method includes the steps of: (a) forming a transistor gate electrode in a portion of an insulating layer formed over a semiconductor substrate, in a buried manner; (b) forming a trench in the semiconductor substrate through a portion of the insulating layer; and (c) forming a transistor channel region, a source, a drain and a capacitor storage node, as a single layer, over a region defined over a transistor gate electrode-buried portion of the insulating layer and a region defined in the trench. Thereby a source, a drain and a gate channel of each transistor and a capacitor storage node are formed by a single layer.

Abstract: A semiconductor device and a method of making the same capable of simplifying the process of making and reducing the cost of making. In the method a first layer is formed which has a plurality of conductors at its edge portion. Thereafter, a second layer is formed on the first layer which is to be selectively etched to form a pattern. During the etching, current is detected from the conductors and the etching is stopped dependent on the current detected from the conductors. The semiconductor device includes a transparent electrode on a substrate the transparent electrode having protrusions which have a top surface. A first insulation layer exists between the protrusions. There is a color emitting layer on the top surfaces of the protrusions and the insulation layer.

Abstract: A DRAM cell and a method for fabricating the same capable of obtaining a large capacitance for achieving a high integration and yet maintaining superior characteristics of elements. A capacitor structure is provided, which includes a common storage node formed at the inner wall of a trench, and two plate electrodes connected to each other in parallel, that is, a substrate and a polysilicon layer formed over the storage node via a second dielectric film and connected to the substrate in parallel. With such a capacitor structure, the capacitance per unit capacitor area can be maximized. A source, a drain and a gate channel of each transistor and a capacitor storage node are formed by a single layer. With this structure, a minimum information transmitting path is obtained, thereby enabling the overall structure and the fabrication therefor to be simplified. Furthermore, the present invention makes it easy to form an active region where elements are formed, without using an element isolation process.

Abstract: A semiconductor device and a method of making the same capable of simplifying the process of making and reducing the cost of making. In the method a first layer is formed which has a plurality of conductors at its edge portion. Thereafter, a second layer is formed on the first layer which is to be selectively etched to form a pattern. During the etching, current is detected from the conductors and the etching is stopped dependent on the current detected from the conductors. The semiconductor device includes a transparent electrode on a substrate the transparent electrode having protrusions which have a top surface. A first insulation layer exists between the protrusions. There is a color emitting layer on the top surfaces of the protrusions and the insulation layer.

Abstract: Methods of making semiconductor memory cells and semiconductor memory devices capable of improving the degree of integration and simplifying the overall manufacturing processes. Within a substrate made of a semiconductor material or an insulating material, at least one trench is formed to provide a capacitor region. In the trench are formed a plate electrode, a capacitor dielectric layer and a storage node electrode which constitute a capacitor. The semiconductor substrate may be used as the plate electrode. In this case, the trench has only the capacitor dielectric layer and the storage node electrode. At the inlet of the trench filled with the constituting elements of the capacitor, a gate electrode and a semiconductor layer as an active layer are formed to extend vertically perpendicular to the trench inlet. A bit line contact is formed on the semiconductor layer. Over the bit line contact are formed a bit line contact and a bit line, in this order.