Abstract: A storage device having a multi drop structure is provided. The storage device comprises a storage controller configured to output a data signal, a first non-volatile memory configured to receive the data signal, a first wiring electrically connected to the storage controller and configured to transfer the data signal, a first termination module including a first impedance element that electrically connects the first wiring to at least one of a power voltage or a ground voltage, a second wiring electrically connected to the first wiring and configured to transfer the data signal to the first non-volatile memory, and a third wiring electrically connected to the first wiring and configured to transfer the data signal to the first termination module.

Abstract: A method for decoding an image based on an intra prediction, comprising: obtaining a first prediction pixel of a first region in a current block by using a neighboring pixel adjacent to the current block; obtaining a second prediction pixel of a second region in the current block by using the first prediction pixel of the first region; and decoding the current block based on the first and the second prediction pixels.

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

Abstract: An out-of-band management method for a storage apparatus includes communicating with a micro controller unit of the storage apparatus by a baseboard management controller to obtain product information of the storage apparatus or status information of the storage apparatus and operating the storage apparatus by the baseboard management controller based on the obtained information.

Abstract: Disclosed is an electronic device which includes a plurality of memory devices, a memory controller, a first signal line that makes electrical connection between the memory controller and a first branch point, a second signal line that makes electrical connection between the first branch point and a second branch point, a third signal line that makes electrical connection between the first branch point and a third branch point, a fourth signal line that electrically connects the second branch point and the first memory device, a fifth signal line that electrically connects the second branch point and the second memory device, a sixth signal line that electrically connects the third branch point and the third memory device, and a stub that includes a first end electrically connected with at least one of the plurality of signal lines, and a second end being left open-circuit.

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

Abstract: A power supply circuit includes a first comparator, a second comparator, a first voltage regulator, an output terminal, a first path and a second path. The first comparator compares a first input voltage with a first reference voltage to generate a first control signal. The second comparator compares a second input voltage with the first reference voltage to generate a second control signal. A voltage level of the second input voltage is different from a voltage level of the first input voltage. The first voltage regulator is selectively enabled based on the first control signal and the second control signal, and generates a first voltage based on the first input voltage. A voltage level of the first voltage is substantially the same as the voltage level of the second input voltage. The output terminal is configured to output one of the second input voltage and the first voltage as a power supply voltage. The first path directly provides the first input voltage to the first voltage regulator.

Abstract: A power supply circuit includes a first comparator, a second comparator, a first voltage regulator, an output terminal, a first path and a second path. The first comparator compares a first input voltage with a first reference voltage to generate a first control signal. The second comparator compares a second input voltage with the first reference voltage to generate a second control signal. A voltage level of the second input voltage is different from a voltage level of the first input voltage. The first voltage regulator is selectively enabled based on the first control signal and the second control signal, and generates a first voltage based on the first input voltage. A voltage level of the first voltage is substantially the same as the voltage level of the second input voltage. The output terminal is configured to output one of the second input voltage and the first voltage as a power supply voltage. The first path directly provides the first input voltage to the first voltage regulator.

Abstract: A power supply circuit includes a first comparator, a second comparator, a first voltage regulator, an output terminal, a first path and a second path. The first comparator compares a first input voltage with a first reference voltage to generate a first control signal. The second comparator compares a second input voltage with the first reference voltage to generate a second control signal. A voltage level of the second input voltage is different from a voltage level of the first input voltage. The first voltage regulator is selectively enabled based on the first control signal and the second control signal, and generates a first voltage based on the first input voltage. A voltage level of the first voltage is substantially the same as the voltage level of the second input voltage. The output terminal is configured to output one of the second input voltage and the first voltage as a power supply voltage. The first path directly provides the first input voltage to the first voltage regulator.

Abstract: A power supply circuit includes a first comparator, a second comparator, a first voltage regulator, an output terminal, a first path and a second path. The first comparator compares a first input voltage with a first reference voltage to generate a first control signal. The second comparator compares a second input voltage with the first reference voltage to generate a second control signal. A voltage level of the second input voltage is different from a voltage level of the first input voltage. The first voltage regulator is selectively enabled based on the first control signal and the second control signal, and generates a first voltage based on the first input voltage. A voltage level of the first voltage is substantially the same as the voltage level of the second input voltage. The output terminal is configured to output one of the second input voltage and the first voltage as a power supply voltage. The first path directly provides the first input voltage to the first voltage regulator.

Abstract: Methods of programming firmware in a data storage device include pre-programming memory cells included in at least one nonvolatile memory of a plurality of nonvolatile memories using a first verification voltage higher than a first reference voltage before a surface mounting technology is applied to the nonvolatile memories.

Abstract: Methods of programming firmware in a data storage device include pre-programming memory cells included in at least one nonvolatile memory of a plurality of nonvolatile memories using a first verification voltage higher than a first reference voltage before a surface mounting technology is applied to the nonvolatile memories.

Abstract: A memory system includes a package having a memory device, and a wiring board to which the package is attached. The wiring board includes a first region and a second region separable from the first region. The first region may conform in terms of its dimensions and other physical characteristics to a first form factor of the memory system, and the first and second regions collectively may conform in the same way to a second form factor of the memory system.

Abstract: A method and apparatus for compensating for a disturbance by detecting a periodic external disturbance applied to a data storage apparatus is provided. The method includes: calculating a correlation coefficient for a first signal corresponding to a first period and a second period that is adjacent to the first period generated from a servo control system of a data storage apparatus; estimating a disturbance of a third period by using the first signal of the first period; determining whether a periodic external shock is generated based on the calculated correlation coefficient; and if it is determined that the periodic external shock is generated, compensating for the disturbance to be generated in the third period by feed-forwarding the estimated disturbance of the third period to the servo control system.