Abstract: A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.

Abstract: A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.

Abstract: A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.

Abstract: A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer, etching the hard mask layer to form a first and a second hard mask pattern in the first and the second regions, respectively, reducing a width of the second hard mask pattern formed in the second region and etching the etch target layer using the first hard mask pattern and the second hard mask pattern having the reduced width as an etch barrier to form the etch target patterns in the first and the second regions.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.

Abstract: A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.

Abstract: A method for fabricating a semiconductor device includes forming a storage node contact plug over a cell region of a substrate, forming a first inter-layer dielectric layer over the substrate, forming a first bit line over the first inter-layer dielectric layer in a peripheral region of the substrate, forming a second inter-layer dielectric layer over the first inter-layer dielectric layer, forming a second bit line over the second inter-layer dielectric layer, etching the second inter-layer dielectric layer to expose an upper surface of the storage node contact plug in the cell region, forming a capacitor contacting the storage node contact plug, forming a third inter-layer dielectric layer over the substrate having the capacitor formed thereon, forming a metal contact through the third inter-layer dielectric layer to contact the second bit line in the peripheral region, and forming a metal line contacting the metal contact over the third inter-layer dielectric layer.

Abstract: A method for fabricating a semiconductor device includes depositing and stacking a hard mask layer and a sacrificial layer over an etch target layer forming a mask pattern with holes defined therein over the sacrificial layer, forming first pillars filling the holes; removing the mask pattern, forming second pillars by using the first pillars as an etch barrier and etching the sacrificial layer, forming spacers surrounding sidewalls of each second pillar, removing the second pillars, etching the hard mask layer by using the spacers as etch barriers to form a hard mask pattern, and forming a hole pattern by using the hard mask pattern as an etch barrier and etching the etch target layer.

Abstract: A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging.

Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first trench pattern, forming spacers over sidewalls of the first trench pattern, etching a bottom portion of the first trench pattern using the spacers as a barrier to form a second trench pattern, performing an isotropic etching on the second trench pattern to round sidewalls of the second trench pattern and form a bulb pattern, and forming a gate over a recess pattern including the first trench pattern, the rounded second trench pattern and the bulb pattern.

Abstract: An etching method in a semiconductor device includes forming a nitride-based first hard mask layer over a target etch layer, forming a carbon-based second hard mask pattern over the first hard mask layer, etching the first hard mask layer using the second hard mask pattern as an etch barrier to form a first hard mask pattern, cleaning a resultant structure including the first hard mask pattern, and etching the target etch layer using the second hard mask pattern as an etch barrier.

Abstract: A method for fabricating a semiconductor device includes forming a sacrificial layer having a stack structure of a first insulation layer, a first conductive layer and a second insulation layer over a substrate, forming a recess by etching the sacrificial layer and the substrate, forming a gate insulation layer over a recess surface, filling a second conductive layer in the recess and between etched sacrificial layers, forming a gate electrode metal layer, a gate hard mask layer and a gate mask pattern over a resultant substrate, etching layers formed below the gate mask pattern by using the gate mask pattern until the first conductive layer is exposed, thereby forming an initial gate pattern, forming a capping layer on a sidewall and a top portion of the initial gate pattern, and etching an exposed portion by using the capping layer as a mask until the first insulation layer is exposed, thereby forming a final gate pattern.

Abstract: A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging.

Abstract: A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom

Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.

Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.