Patents by Inventor Jae-Soo Ahn

Jae-Soo Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060270228
    Abstract: A method of forming a metal pattern using a selective electroplating process is provided. First, a dielectric layer is formed on an underlying layer. Then, a trench defining blanket region is formed by patterning the dielectric layer. A diffusion barrier layer is conformally formed in the trench and on the blanket region. A polishing/plating stop layer and an upper seed layer are conformally formed on the diffusion barrier layer in a successive manner. The polishing/plating layer in the blanket region is exposed by selectively removing the upper seed layer in the blanket region, and, at the same time, a seed layer pattern remaining in the trenches is formed. An upper conductive layer is formed to fill the trench surrounded by the seed layer pattern using an electroplating process. Then, the dielectric layer in the blanket region is exposed by planarizing the upper conductive layer, the polishing/plating stop layer, the seed layer pattern, and the diffusion barrier layer.
    Type: Application
    Filed: August 9, 2006
    Publication date: November 30, 2006
    Inventors: Hyo-Jong Lee, Jong-Won Lee, Duk-Ho Hong, Sang-Rok Hah, Hong-Seong Son, Jin-Sung Chung, Jae-Soo Ahn
  • Publication number: 20050070090
    Abstract: A method of forming a metal pattern using a selective electroplating process is provided. First, a dielectric layer is formed on an underlying layer. Then, a trench defining blanket region is formed by patterning the dielectric layer. A diffusion barrier layer is conformally formed in the trench and on the blanket region. A polishing/plating stop layer and an upper seed layer are conformally formed on the diffusion barrier layer in a successive manner. The polishing/plating layer in the blanket region is exposed by selectively removing the upper seed layer in the blanket region, and, at the same time, a seed layer pattern remaining in the trenches is formed. An upper conductive layer is formed to fill the trench surrounded by the seed layer pattern using an electroplating process. Then, the dielectric layer in the blanket region is exposed by planarizing the upper conductive layer, the polishing/plating stop layer, the seed layer pattern, and the diffusion barrier layer.
    Type: Application
    Filed: June 24, 2004
    Publication date: March 31, 2005
    Inventors: Hyo-Jong Lee, Jong-Won Lee, Duk-Ho Hong, Sang-Rok Hah, Hong-Seong Son, Jin-Sung Chung, Jae-Soo Ahn