Abstract: An electronic display panel comprising a plastic substrate; a bottom shield metal (BSM) on the plastic substrate; a thin-film transistor (TFT) on the BSM, the TFT and the BSM at least partially overlapping each other; and an active buffer layer between the TFT and the BSM, wherein the BSM is connected to one of a gate electrode, a source electrode, and a drain electrode of the TFT. A bottom shield metal (BSM) on the plastic substrate, the BSM located to minimize formation of a back channel in a pixel circuit by trapped charges of the plastic substrate, the pixel circuit in a pixel area defined by a gate line and a data line on the plastic substrate, the pixel circuit on the active buffer layer including a plurality of TFTs and a plurality of component interconnecting nodes.

Abstract: An electronic display panel comprising a plastic substrate; a bottom shield metal (BSM) on the plastic substrate; a thin-film transistor (TFT) on the BSM, the TFT and the BSM at least partially overlapping each other; and an active buffer layer between the TFT and the BSM, wherein the BSM is connected to one of a gate electrode, a source electrode, and a drain electrode of the TFT. A bottom shield metal (BSM) on the plastic substrate, the BSM located to minimize formation of a back channel in a pixel circuit by trapped charges of the plastic substrate, the pixel circuit in a pixel area defined by a gate line and a data line on the plastic substrate, the pixel circuit on the active buffer layer including a plurality of TFTs and a plurality of component interconnecting nodes.

Abstract: A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.

Abstract: An electrophoretic display (EPD) device adapted to prevent a dispensed fluid sealant from moving toward a non-active area is disclosed. The EPD device includes: a first substrate configured to include a flexible plate divided into an active area and a non-active area; a thin film transistor array formed on the active area of the plate; a second substrate opposite to the first substrate; an electrophoretic film, between the first and second substrates, configured to contain charged particles driven depending on electrophoresis; a sealant, between the first and second substrates, hardened from fluid state; a sealant block formed on a sealant formation region to prevent the fluid sealant from flowing into the non-active area before hardening of the fluid sealant, wherein the sealant block is configured to include a first dam, a second dam, and a furrow between the first and second dams.

Abstract: Disclosed is an electrophoretic display (EPD) device capable of delaying or preventing a sealant from leaking down by forming a dam pattern prior to a sealing process using the sealant, and a method for fabricating the same. The EPD device comprises: gate lines and data lines crossing each other to define a pixel region, and formed on a lower substrate; a thin film transistor (TFT) electrically connected to the gate lines and the data lines; a passivation film covering the TFT; a pixel electrode electrically connected to the TFT; a display layer formed on the pixel electrode and the passivation film, and having an electrophoretic substance; a common electrode formed on an entire surface of the display layer; an upper substrate formed on the common electrode; a seal pattern formed on each outer circumferential surface of the lower substrate, the upper substrate, and the display layer; and a dam pattern formed on the lower substrate adjacent to the seal pattern.

Abstract: An electrophoretic display (EPD) device adapted to prevent a dispensed fluid sealant from moving toward a non-active area is disclosed. The EPD device includes: a first substrate configured to include a flexible plate divided into an active area and a non-active area; a thin film transistor array formed on the active area of the plate; a second substrate opposite to the first substrate; an electrophoretic film, between the first and second substrates, configured to contain charged particles driven depending on electrophoresis; a sealant, between the first and second substrates, hardened from fluid state; a sealant block formed on a sealant formation region to prevent the fluid sealant from flowing into the non-active area before hardening of the fluid sealant, wherein the sealant block is configured to include a first dam, a second dam, and a furrow between the first and second dams.

Abstract: In an apparatus for curing a seal in an electrophoretic display device according to the present invention, a support having magnetism may be provided on a curing table to be loaded with an electrophoretic display device in order to support the electrophoretic display device while at the same time generating a magnetic force in a direction opposite to a stress caused by a seal material in the electrophoretic display device, thereby preventing the electrophoretic display device from being bent when the seal material is cured.

Abstract: Disclosed is an electrophoretic display (EPD) device capable of delaying or preventing a sealant from leaking down by forming a dam pattern prior to a sealing process using the sealant, and a method for fabricating the same. The EPD device comprises: gate lines and data lines crossing each other to define a pixel region, and formed on a lower substrate; a thin film transistor (TFT) electrically connected to the gate lines and the data lines; a passivation film covering the TFT; a pixel electrode electrically connected to the TFT; a display layer formed on the pixel electrode and the passivation film, and having an electrophoretic substance; a common electrode formed on an entire surface of the display layer; an upper substrate formed on the common electrode; a seal pattern formed on each outer circumferential surface of the lower substrate, the upper substrate, and the display layer; and a dam pattern formed on the lower substrate adjacent to the seal pattern.

Abstract: An integrated circuit interconnect is provided having a dielectric layer disposed between a wide top metal line and a wide bottom metal line. A via-sea in the dielectric layer connects the wide top and wide bottom metal lines by means of a first via having a width, a second via having a width and spaced more than two widths away and less than four widths away from the first via.

Abstract: A method is provided for an integrated circuit interconnect having a dielectric layer disposed between a wide top metal line and a wide bottom metal line. A via-sea in the dielectric layer connects the wide top and wide bottom metal lines by means of a first via having a width, a second via having a width and spaced more than a width away and less than four widths away from the first via. The width and spacing of the vias reduce the occurrence of metal explosions which are known to reduce the power carrying capability of the power lines and adversely affect the performance of the devices in the integrated circuit.