Patents by Inventor Jae-sub KIM
Jae-sub KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250069432Abstract: Disclosed herein are a facial recognition method and apparatus based on masking. The facial recognition method based on masking includes performing detection and normalization of a face area including five landmarks in an input image, separating a face portion other than a portion covered by an obstacle in the detected face area, generating a mask corresponding to the separated face portion when there is a portion covered by an obstacle in the separated face portion, applying the mask to an image in a face image registration database and extracting a feature of a masking region, and determining whether it is an identical person based on the extracted feature value.Type: ApplicationFiled: February 6, 2024Publication date: February 27, 2025Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ho-Sub YOON, Jae-Hong KIM, Jae-Yoon JANG
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Patent number: 12230924Abstract: A connector structure according to an embodiment of the present disclosure includes a second connector and a first connector coupled to the second connector. The first connector includes a first insulator, a first conductive connection terminal disposed on the first insulator, a second conductive connection terminal spaced apart from the first conductive connection terminal to form a single row structure on the first insulator together with the first conductive connection terminal, and a first barrier structure disposed between the first conductive connection terminal and the second conductive connection terminal on the first insulator.Type: GrantFiled: February 16, 2022Date of Patent: February 18, 2025Assignee: DONGWOO FINE-CHEM CO., LTD.Inventors: Young Ju Kim, Byung Jin Choi, Han Sub Ryu, Na Yeon Kim, Dong Pil Park, Jae Hyun Lee
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Patent number: 12221022Abstract: Provided is a duct docking device for a ventilation seat of a vehicle. The duct docking device enables air to be easily blown to a seatback and a seat cushion with a passenger in a seat using only one blower by enabling a seatback duct mounted at the seatback and a seat cushion duct mounted at the seat cushion to be hermetically docked through a connector duct, etc. at an unfolded position of the seatback in which a passenger can sit, and by enabling the seatback duct mounted at the seatback and the seat cushion duct mounted at the seat cushion to be separated from each other at a folded position of the seatback in consideration of that there is no passenger in the seat.Type: GrantFiled: December 21, 2022Date of Patent: February 11, 2025Assignees: Hyundai Motor Company, Kia Corporation, Hyundai Transys Inc.Inventors: Deok Soo Lim, Sang Hark Lee, Sang Soo Lee, Jung Sang You, Sang Do Park, Chan Ho Jung, Gun Chu Park, Gi Tae Jo, Jin Sik Kim, Hee Dong Yoon, Ho Sub Lim, Jae Hyun Park
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Publication number: 20250038199Abstract: A cathode active material for an all-solid-state battery includes: active material particles; and a coating layer covering at least a portion of the surface of the active material particles, wherein the coating layer includes lithium (Li), niobium (Nb), and at least one element selected from the group consisting of vanadium (V), zirconium (Zr) and combinations thereof.Type: ApplicationFiled: October 10, 2024Publication date: January 30, 2025Applicants: HYUNDAI MOTOR COMPANY, Kia Corporation, Ulsan National Institute of Science and TechnologyInventors: A Reum Ha, Ju Yeong Seong, Yong Gu Kim, In Woo Song, Hong Seok Min, Yong Sub Yoon, Yun Sung Kim, Sung Woo Noh, Yong Jun Jang, Sang Heon Lee, Jae Phil Cho, Hyo Myoung Lee
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Patent number: 11842075Abstract: A storage device comprises a nonvolatile memory configured to store data that is written in size units of a mapping size, and a storage controller configured to transmit a command to the nonvolatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapping size. The storage controller includes processing circuitry configured to transmit a read command to the nonvolatile memory, to cause the nonvolatile memory to read second data stored in the nonvolatile memory addressed based on the first address, in response to a determination that the first size is smaller than the mapping size and before the first data is received at the storage controller through the host interface.Type: GrantFiled: August 25, 2021Date of Patent: December 12, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Yun Seok Kang, Jae Sub Kim, Yang Woo Roh, Jeong Beom Seo, Kyung Wook Ye
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Patent number: 11789652Abstract: A storage device includes a non-volatile memory; a plurality of cores; a host interface configured to receive a first set command, an I/O command, and an ADMIN command from a host; and a storage controller including a command distribution module configured to be set to a first state according to the first set command, and distribute the I/O command to the plurality of cores according to the set first state. Each of the plurality of cores may be configured to perform an operation instructed by the I/O command and an operation instructed by the ADMIN command on the non-volatile memory in response to the distributed I/O command.Type: GrantFiled: July 28, 2021Date of Patent: October 17, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Bum Hoe Koo, Jae Sub Kim, Yang Woo Roh, Dong Heon Ryu
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Patent number: 11733882Abstract: A memory device executes a method of controlling power of the memory device. The memory device includes a host interface which receives a command from a host and controls an access to the memory device by the host, a register which is accessible by the host and includes a plurality of different regions, a memory access monitor which monitors which region of the plurality of regions the host accesses, and in response thereto generates a monitoring signal, and a power control manager which selects a power-up group of modules of the memory device in accordance with the monitoring signal and which supplies power to the selected power-up group of modules while not supplying power to any modules of the memory device not belonging to the selected power-up group.Type: GrantFiled: November 10, 2020Date of Patent: August 22, 2023Inventors: Nam-Hoon Kim, Jae Sub Kim, Jae Won Song, Se Jeong Jang
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Publication number: 20220236915Abstract: A storage device comprises a nonvolatile memory configured to store data that is written in size units of a mapping size, and a storage controller configured to transmit a command to the nonvolatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapping size. The storage controller includes processing circuitry configured to transmit a read command to the nonvolatile memory, to cause the nonvolatile memory to read second data stored in the nonvolatile memory addressed based on the first address, in response to a determination that the first size is smaller than the mapping size and before the first data is received at the storage controller through the host interface.Type: ApplicationFiled: August 25, 2021Publication date: July 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Yun Seok KANG, Jae Sub KIM, Yang Woo ROH, Jeong Beom SEO, Kyung Wook YE
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Publication number: 20220156007Abstract: A storage device includes a non-volatile memory; a plurality of cores; a host interface configured to receive a first set command, an I/O command, and an ADMIN command from a host; and a storage controller including a command distribution module configured to be set to a first state according to the first set command, and distribute the I/O command to the plurality of cores according to the set first state. Each of the plurality of cores may be configured to perform an operation instructed by the I/O command and an operation instructed by the ADMIN command on the non-volatile memory in response to the distributed I/O command.Type: ApplicationFiled: July 28, 2021Publication date: May 19, 2022Inventors: Bum Hoe KOO, Jae Sub KIM, Yang Woo ROH, Dong Heon RYU
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Publication number: 20210055871Abstract: A memory device executes a method of controlling power of the memory device. The memory device includes a host interface which receives a command from a host and controls an access to the memory device by the host, a register which is accessible by the host and includes a plurality of different regions, a memory access monitor which monitors which region of the plurality of regions the host accesses, and in response thereto generates a monitoring signal, and a power control manager which selects a power-up group of modules of the memory device in accordance with the monitoring signal and which supplies power to the selected power-up group of modules while not supplying power to any modules of the memory device not belonging to the selected power-up group.Type: ApplicationFiled: November 10, 2020Publication date: February 25, 2021Inventors: NAM-HOON KIM, JAE SUB KIM, JAE WON SONG, SE JEONG JANG
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Patent number: 10866748Abstract: A memory device executes a method of controlling power of the memory device. The memory device includes a host interface which receives a command from a host and controls an access to the memory device by the host, a register which is accessible by the host and includes a plurality of different regions, a memory access monitor which monitors which region of the plurality of regions the host accesses, and in response thereto generates a monitoring signal, and a power control manager which selects a power-up group of modules of the memory device in accordance with the monitoring signal and which supplies power to the selected power-up group of modules while not supplying power to any modules of the memory device not belonging to the selected power-up group.Type: GrantFiled: May 21, 2018Date of Patent: December 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Hoon Kim, Jae Sub Kim, Jae Won Song, Se Jeong Jang
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Patent number: 10466938Abstract: A method of operating a non-volatile memory system, the method comprising: receiving an access request from a host; generating internal requests by processing the access request by a first central processing unit (CPU) according to a first mapping unit having a first size; and accessing a memory by processing the internal requests by a second CPU according to a second mapping unit having a second size; wherein the first size is different from the second size.Type: GrantFiled: May 17, 2016Date of Patent: November 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-young Seo, Jae-sub Kim
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Publication number: 20190146695Abstract: A memory device executes a method of controlling power of the memory device. The memory device includes a host interface which receives a command from a host and controls an access to the memory device by the host, a register which is accessible by the host and includes a plurality of different regions, a memory access monitor which monitors which region of the plurality of regions the host accesses, and in response thereto generates a monitoring signal, and a power control manager which selects a power-up group of modules of the memory device in accordance with the monitoring signal and which supplies power to the selected power-up group of modules while not supplying power to any modules of the memory device not belonging to the selected power-up group.Type: ApplicationFiled: May 21, 2018Publication date: May 16, 2019Inventors: NAM-HOON KIM, JAE SUB KIM, JAE WON SONG, SE JEONG JANG
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Publication number: 20170052901Abstract: A method of operating a non-volatile memory system, the method comprising: receiving an access request from a host; generating internal requests by processing the access request by a first central processing unit (CPU) according to a first mapping unit having a first size; and accessing a memory by processing the internal requests by a second CPU according to a second mapping unit having a second size; wherein the first size is different from the second size.Type: ApplicationFiled: May 17, 2016Publication date: February 23, 2017Inventors: Dong-young SEO, Jae-sub KIM