Patents by Inventor Jae-Sung Rieh
Jae-Sung Rieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140077897Abstract: A resonator fabrication method is provided. A method includes providing a plurality of electrode patterns disposed apart from each other on a substrate using a nano-imprint technique; and forming an extended electrode pattern connected to a plurality of electrode patterns, and forming a nano structure laid across an extended electrode patterns. Therefore, a nano-electromechanical system (NEMS) resonator is easily fabricated at a nanometer level.Type: ApplicationFiled: November 1, 2013Publication date: March 20, 2014Applicants: KOREA UNIVERSITY INDUSTRIAL AND ACADEMIC COLLABORATION FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-kwon PARK, Byeoung-ju HA, Byeong-Kwon Ju, Jae-sung RIEH, In-sang SONG, Jin-woo LEE, Jea-shik SHIN, Young-min PARK
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Patent number: 8659098Abstract: A resonator fabrication method is provided. A method includes providing a plurality of electrode patterns disposed apart from each other on a substrate using a nano-imprint technique; and forming an extended electrode pattern connected to a plurality of electrode patterns, and forming a nano structure laid across an extended electrode patterns. Therefore, a nano-electromechanical system (NEMS) resonator is easily fabricated at a nanometer level.Type: GrantFiled: February 18, 2009Date of Patent: February 25, 2014Assignees: Samsung Electronics Co., Ltd., Korea University Industrial and Academic Collaboration FoundationInventors: Yun-Kwon Park, Byeoung-Ju Ha, Byeong-Kwon Ju, Jae-Sung Rieh, In-Sang Song, Jin-Woo Lee, Jea-Shik Shin, Young-Min Park
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Publication number: 20120126327Abstract: A resonator and a method for manufacturing a resonator are provided. The method may include doping a wafer, and forming on the wafer a substrate, a drain electrode, a source electrode, a gate electrode, and at least one nanowire.Type: ApplicationFiled: November 22, 2011Publication date: May 24, 2012Applicants: KOREA UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: In Sang SONG, Sung Woo HWANG, Yun Kwon PARK, Byeong Kwon JU, Jae Sung RIEH, Jea Shik SHIN, Hee Tae KIM
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Patent number: 8120015Abstract: A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.Type: GrantFiled: January 22, 2009Date of Patent: February 21, 2012Assignees: Samsung Electronics Co., Ltd., Korea University Industrial and Academic Collaboration FoundationInventors: Yun-Kwon Park, Sung-Woo Hwang, Jea-Shik Shin, Byeoung-Ju Ha, Jae-Sung Rieh, In-Sang Song, Yong-Kyu Kim, Byeong-Kwon Ju, Hee-Tae Kim
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Patent number: 8089316Abstract: A broadband active circuit with a feedback structure includes: an active load unit providing a load varied according to a control voltage; an active circuit unit connected between the active load unit and a ground and outputting a signal corresponding to a pre-set bandwidth, among input signals; and a feedback circuit unit formed between an output terminal of the active circuit unit and the active load unit and providing a signal from the output terminal of the active circuit unit to the active load unit.Type: GrantFiled: December 23, 2009Date of Patent: January 3, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Chul Gyun Park, Jae Sung Rieh, Dong Hyun Kim
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Patent number: 7989868Abstract: A MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, includes: gate insulating layers arranged at equal intervals in the form of a (n×m) matrix, and a gate electrode placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire, which is electrically connected to the gate contact; source/drain contacts arranged at equal intervals in a matrix to form apexes of a square centered at the gate electrode and contact a doping region except for the bottom of the gate insulating layers; and a second metal wire, which is electrically connected to the source/drain contacts.Type: GrantFiled: September 23, 2009Date of Patent: August 2, 2011Assignee: Korea University Industrial & Academic Collaboration FoundationInventors: Jae-Sung Rieh, Yong Ho Oh, Sue Yeon Kim, Seung Yong Lee
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Publication number: 20110084766Abstract: A broadband active circuit with a feedback structure includes: an active load unit providing a load varied according to a control voltage; an active circuit unit connected between the active load unit and a ground and outputting a signal corresponding to a pre-set bandwidth, among input signals; and a feedback circuit unit formed between an output terminal of the active circuit unit and the active load unit and providing a signal from the output terminal of the active circuit unit to the active load unit.Type: ApplicationFiled: December 23, 2009Publication date: April 14, 2011Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Chul Gyun Park, Jae Sung Rieh, Dong Hyun Kim
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Publication number: 20100244113Abstract: The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor.Type: ApplicationFiled: September 23, 2009Publication date: September 30, 2010Applicant: KOREA UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATIONInventors: Jae-Sung Rieh, Yong Ho Oh, Sue Yeon Kim, Seung Yong Lee
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Patent number: 7709930Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.Type: GrantFiled: April 22, 2004Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Andreas Stricker, David Sheridan, Jae-Sung Rieh, Gregory Freeman, Steven Voldman, Stephen A. St. Onge
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Patent number: 7696034Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: GrantFiled: May 28, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, Beth Ann Rainey, Jae-Sung Rieh, Andreas D. Stricker
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Patent number: 7622357Abstract: The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first conductive contact is located over the front surface of the substrate and laterally offset from the first conductive structure. The first conductive contact is electrically connected to the first conductive structure by a conductive path that extends: (1) from the first conductive structure through the substrate to the back surface, (2) across the back surface, and (3) from the back surface through the substrate to the first conductive contact on the front surface. Further, a second conductive contact is located over the front surface and is electrically connected to the second conductive structure. The conductive path can be formed by lithography and etching followed by metal deposition.Type: GrantFiled: May 25, 2006Date of Patent: November 24, 2009Assignee: International Business Machines CorporationInventors: Kunal Vaed, Jae-Sung Rieh, Richard P. Volant, Francois Pagette
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Publication number: 20090267706Abstract: A resonator fabrication method is provided. A method includes providing a plurality of electrode patterns disposed apart from each other on a substrate using a nano-imprint technique; and forming an extended electrode pattern connected to a plurality of electrode patterns, and forming a nano structure laid across an extended electrode patterns. Therefore, a nano-electromechanical system (NEMS) resonator is easily fabricated at a nanometer level.Type: ApplicationFiled: February 18, 2009Publication date: October 29, 2009Applicants: SAMSUNG ELECTRONICS CO., LTD., KOREA UNIVERSITY INDUSTRIAL & ACADEMIC COLLABORATION FOUNDATIONInventors: Yun-kwon PARK, Byeoung-Ju Ha, Byeong-Kwon Ku, Jae-Sung Rieh, In-Sang Song, Jin-Woo Lee, Jea-shik Shin, Young-Min Park
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Publication number: 20090184783Abstract: A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.Type: ApplicationFiled: January 22, 2009Publication date: July 23, 2009Applicants: SAMSUNG ELECTRONICS CO., LTD., KOREA UNIVERSITY INDUSTRIAL AND ACADEMIC COLLABORATION FOUNDATIONInventors: Yun-kwon Park, Sung-Woo Hwang, Jea-Shik Shin, Byeoung-Ju Ha, Jae-Sung Rieh, In-Sang Song, Yong-Kyu Kim, Byeong-Kwon Ju, Hee-Tae Kim
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Publication number: 20080268604Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: ApplicationFiled: May 28, 2008Publication date: October 30, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas D. Stricker
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Patent number: 7390721Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: GrantFiled: September 21, 2005Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas D. Stricker
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Publication number: 20070275533Abstract: The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first conductive contact is located over the front surface of the substrate and laterally offset from the first conductive structure. The first conductive contact is electrically connected to the first conductive structure by a conductive path that extends: (1) from the first conductive structure through the substrate to the back surface, (2) across the back surface, and (3) from the back surface through the substrate to the first conductive contact on the front surface. Further, a second conductive contact is located over the front surface and is electrically connected to the second conductive structure. The conductive path can be formed by lithography and etching followed by metal deposition.Type: ApplicationFiled: May 25, 2006Publication date: November 29, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kunal Vaed, Jae-Sung Rieh, Richard P. Volant, Francois Pagette
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Patent number: 7288827Abstract: A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation.Type: GrantFiled: October 20, 2004Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Huajie Chen, Kathryn T. Schonenberg, Gregory G. Freeman, Andreas D. Stricker, Jae-Sung Rieh
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Publication number: 20070215978Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.Type: ApplicationFiled: April 22, 2004Publication date: September 20, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andreas Stricker, David Sheridan, Jae-Sung Rieh, Greg Freeman, Steven Voldman, Stephen Onge
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Publication number: 20060017066Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: ApplicationFiled: September 21, 2005Publication date: January 26, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Geiss, Marwan Khater, Qizhi Liu, Randy Mann, Robert Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas Stricker
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Patent number: 6965133Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.Type: GrantFiled: March 13, 2004Date of Patent: November 15, 2005Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Marwan H. Khater, Qizhi Liu, Randy W. Mann, Robert J. Purtell, BethAnn Rainey, Jae-Sung Rieh, Andreas D. Stricker