Abstract: A memory device and a method of manufacturing the memory device are described. The memory device includes a connection structure formed on a substrate, lower contacts formed on the connection structure, upper contacts formed on the lower contacts, a dummy pattern configured to enclose the lower contacts and spaced apart from the lower contacts, etching stop patterns formed in an upper region of the dummy pattern, and dummy contacts formed over the etching stop patterns.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked on a substrate in a vertical direction, a channel structure penetrating at least a portion of the gate stacked body and having a first end protruding upward higher than the gate stacked body, a memory layer enclosing a sidewall of the channel structure, and a source layer formed on the gate stacked body. The channel structure includes a core insulating layer formed in a central region of the channel structure and extending in a vertical direction, and a channel layer enclosing a sidewall of the core insulating layer and formed to be higher than the core insulating layer and the memory layer in the vertical direction.

Abstract: A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

Abstract: Provided herein may be a memory device and a method of manufacturing the memory device. The memory device may include a connection structure formed on a substrate, lower contacts formed on the connection structure, upper contacts formed on the lower contacts, a dummy pattern configured to enclose the lower contacts and spaced apart from the lower contacts, etching stop patterns formed in an upper region of the dummy pattern, and dummy contacts formed over the etching stop patterns.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked on a substrate in a vertical direction, a channel structure penetrating at least a portion of the gate stacked body and having a first end protruding upward higher than the gate stacked body, a memory layer enclosing a sidewall of the channel structure, and a source layer formed on the gate stacked body. The channel structure includes a core insulating layer formed in a central region of the channel structure and extending in a vertical direction, and a channel layer enclosing a sidewall of the core insulating layer and formed to be higher than the core insulating layer and the memory layer in the vertical direction.

Abstract: A memory device, and a method of manufacturing the memory device, includes a source structure and a contact plug spaced apart from the source structure. A portion of the source structure facing the contact plug is formed to be concave.

Abstract: A semiconductor device includes a stack disposed over a peripheral circuit. The stack includes alternately stacked insulating layers and sacrificial layers. The semiconductor device also includes a first contact structure penetrating through the stack to connect with the peripheral circuit. The first contact structure includes a protruding part extending outward from a sidewall of the first contact structure. The semiconductor device further includes a second contact structure disposed on the first contact structure. The second contact structure is connected to the protruding part of the first contact structure.

Abstract: A semiconductor device includes a cell stack structure including first cell stack layers and stack conductive layers, which are alternately stacked. The semiconductor device also includes a dummy stack structure including first dummy stack layers and second dummy stack layers, which are alternately stacked. The semiconductor device further includes a cell plug penetrating the cell stack structure and a cell chip guard penetrating the dummy stack structure, wherein the cell chip guard surrounds the cell stack structure and the cell plug. A level of a bottom surface of a cell chip guard is substantially equal to that of a bottom surface of the cell plug.

Abstract: A semiconductor device includes: a cell stack structure including first cell stack layers and stack conductive layers, which are alternately stacked; a cell plug penetrating the cell stack structure; and a cell chip guard surrounding the cell stack structure and the cell plug. The cell chip guard includes a guard semiconductor layer and a guard insulating layer covering a sidewall of the guard semiconductor layer.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a stack structure including interlayer insulating layers conductive layers, which are alternately stacked therein; and a plurality of contact plugs formed vertically on the conductive layers. The stack structure is configured to have a stepped structure, and each of a plurality of steps included in the stepped structure includes at least two interlayer insulating layers, among the interlayer insulating layers, and at least two conductive layers, among the conductive layers. The plurality of contact plugs include at least two contact plugs respectively connected to the at least two conductive layers included in each of the plurality of steps.

Abstract: A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

Abstract: Provided herein are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a lower substrate, a peripheral circuit component located on the lower substrate, a lower bonding layer including a lower capacitor structure, the capacitor structure located on the peripheral circuit component, an upper bonding layer including an upper capacitor structure, the upper bonding layer bonded to the lower bonding layer, a plurality of cells and a dummy insulating layer that are located on the upper bonding layer, and an upper substrate being located on the plurality of cells and the dummy insulating layer, wherein the upper capacitor structure is coupled to the lower capacitor structure.

Abstract: The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

Abstract: A semiconductor device includes: a first memory block having a first block pitch; and a second memory block belonging to a same plane as the first memory block, the second memory block located closer to a plane edge than the first memory block, the plane edge being an edge of the plane, wherein the second memory block has a second block pitch that is larger than the first block pitch.

Abstract: A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

Abstract: A semiconductor device includes a substrate, a source structure disposed on the substrate, and cell stack structures disposed on the source structure. The semiconductor device also includes a dummy stack structure disposed between the cell stack structures on the source structure and vertical barriers disposed between the dummy stack structure and the cell stack structures. The semiconductor device further includes at least one lower protective pattern disposed at a lower portion of the dummy stack structure between the vertical barriers.

Abstract: A semiconductor device includes a gate structure including word lines and select lines, the gate structure including a first pad stepped structure for exposing each of the select lines and a common pad structure for exposing the select lines. The semiconductor device also includes first contact plugs connected to the select lines through the first pad stepped structure, respectively. The semiconductor device further includes one or more common contact plugs connected in common to the select lines through the common pad structure.

Abstract: A semiconductor memory device includes: a substrate; a source stack structure and a source insulating layer disposed over the substrate to be spaced apart from each other; an isolation insulating layer disposed between the source stack structure and the source insulating layer; a first stack structure disposed over the source stack structure; a second stack structure disposed over the source insulating layer; a vertical structure penetrating the first stack structure and a portion of the source stack structure; and a lower contact penetrating the source insulating layer.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.