Abstract: An electronic apparatus including: a communicator configured to wirelessly connect to an access point (AP) to enable wireless communication; a storage configured to store AP connection information for connection to the AP through the communicator; a reader configured to read a direct connection information code from an external device when the direct connection information code for direct wireless connection by the electronic apparatus to the external device is installed on the external device; and a controller configured to establish a direct wireless connection to the external device based on the direct connection information code read by the reader and transmit the AP connection information stored in the storage to the external device which is directly wirelessly connected so the external device connects to the AP based on the AP connection information.

Abstract: A wireless fidelity (Wi-Fi) device and Wi-Fi peer-to-peer (P2P) method of communication which minimizes degradation of performance of a Wi-Fi Station mode operation is provided. A terminal device includes a wireless fidelity (Wi-Fi) module which is connected to an access point (AP) and operates in a Wi-Fi station mode. A controller controls the Wi-Fi module to interrupt the connection to the AP when a Wi-Fi peer-to-peer (P2P) function is executed, and iterates an operation of resuming the connection to the AP after a search operation is performed through each channel while a plurality of channels are sequentially selected. When an external device to perform P2P communication is found in the search operation, the controller controls the Wi-Fi module to perform a listen operation of receiving a signal transmitted from the external device and transmitting a response.

Abstract: A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a data cache controller configured to receive cache requests for the cache banks, each of which including a cache bank identifier, transfer the received cache requests to the respective cache banks according to the cache bank identifiers, and process the cache requests independently from one another.

Abstract: A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.

Abstract: Provided is a memory controller that manages memory access requests between the processor and the memory. In response to the memory controller receiving two or more memory access requests for the same area of memory, the memory controller is configured to stall the memory controller and sequentially process the memory access requests.

Abstract: A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction.

Abstract: Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal.

Abstract: Provided are a computing apparatus and method based on SIMD architecture capable of supporting various SIMD widths without wasting resources. The computing apparatus includes a plurality of configurable execution cores (CECs) that have a plurality of execution modes, and a controller for detecting a loop region from a program, determining a Single Instruction Multiple Data (SIMD) width for the detected loop region, and determining an execution mode of the processor according to the determined SIMD width.

Abstract: A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a data cache controller configured to receive cache requests for the cache banks, each of which including a cache bank identifier, transfer the received cache requests to the respective cache banks according to the cache bank identifiers, and process the cache requests independently from one another.

Abstract: Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal.

Abstract: A technology for controlling a reconfigurable processor is provided. The reconfigurable processor dynamically loads configuration data from a peripheral memory to a configuration memory while a program is being executed, in place of loading all compiled configuration data in advance into the configuration memory when booting commences. Accordingly, a reduction in capacity of a configuration memory may be achieved.

Abstract: A system for protecting contents comprises a first device for storing and reproducing contents purchased by a user; a server for issuing usage rights of contents; and a second device for reproducing contents protection mechanism-applied contents, and if contents to be copied from the first device are not protected by the protection mechanism, obtaining the usage rights from the server and converting the unprotected contents into contents under protection of the protection mechanism. When contents purchased by the user is not protected by the DRM, the DRM-employed reproducing device can obtain usage rights with respect to the corresponding contents from the rights issuer. And then, the purchased contents are converted into the contents that can be protected by the DRM.