Patents by Inventor Jae-un PARK
Jae-un PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240139003Abstract: Provided is a bioresorbable stent including a stent substrate including a bioresorbable polymer and a contrast medium containing an iodine component, coated on the stent substrate. Since the stent according to the present invention is absorbed in and removed from the human body after a predetermined time, it has excellent biodegradability since it has improved radiopacity by iodine contrast medium coating, it has a high radiography contrast and is very efficient even when a procedure is performed with real time radiography, and since it has low foreshortening and high flexibility, radial force, and re-coil, it may be useful for insertion into a blood vessel having a small diameter, an acute occlusive lesion, an imminent occlusive lesion, and the like.Type: ApplicationFiled: May 13, 2022Publication date: May 2, 2024Inventors: Myung Ho JEONG, Dae Sung PARK, Jae Un KIM, Mun Ki KIM, Doo Sun SIM, Kyung Hoon CHO, Dae Young HYUN, Jun Kyu PARK
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Publication number: 20240075920Abstract: A method for controlling driving of a hybrid electric vehicle includes collecting driving data while the hybrid electric vehicle is driven, determining whether the hybrid electric vehicle enters a first mode corresponding to emergency driving of the hybrid electric vehicle or a second mode corresponding to control in preparation for the emergency driving, and controlling the hybrid electric vehicle in accordance with a mode that the hybrid electric vehicle enters among the first mode and the second mode.Type: ApplicationFiled: January 31, 2023Publication date: March 7, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Sung Bae Jeon, Seong Wook Moon, Do Hwa Kim, Gyu Ri Lee, Sung Il Jung, Jae Young Park, Jeong Eun Kim, Hui Un Son
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Patent number: 11263018Abstract: A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.Type: GrantFiled: October 23, 2017Date of Patent: March 1, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-seok Kwon, Jae-un Park, Dong-kwan Suh, Kang-jin Yoon
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Patent number: 10956159Abstract: In a method to execute instructions, at least one instruction executed in a predetermined cycle is acquired based on information included in each of a plurality of instructions, and a code included in the at least one instruction acquired. An instruction is allocated to at least one slot based on the analysis result, and a slot necessary to execute the instruction is selectively used. Accordingly, power consumption of a device using the method may be reduced.Type: GrantFiled: November 26, 2014Date of Patent: March 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Un Park, Suk-Jin Kim, Do-Hyung Kim
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Publication number: 20200272478Abstract: A vector processor is disclosed. The vector processor includes a plurality of register files provided to each of a plurality of single instruction multiple data (SIMD) lanes, storing each of a plurality of pieces of data, and respectively outputting input data to be used in a current cycle among the plurality of pieces of data, a shuffle unit for receiving a plurality of pieces of input data outputted from the plurality of register files, and performing shuffling such that the received plurality of pieces of input data respectively correspond to the plurality of SIMD lanes and outputting the same; and a command execution unit for performing a parallel operation by receiving input data outputted from the shuffle unit.Type: ApplicationFiled: October 23, 2017Publication date: August 27, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-seok KWON, Jae-un PARK, Dong-kwan SUH, Kang-jin YOON
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Patent number: 10481867Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.Type: GrantFiled: October 6, 2017Date of Patent: November 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-un Park, Jong-hun Lee, Ki-seok Kwon, Dong-kwan Suh, Kang-jin Yoon, Jung-uk Cho
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Patent number: 10379866Abstract: An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.Type: GrantFiled: July 19, 2017Date of Patent: August 13, 2019Assignee: Samsung Electronics Co., LtdInventors: Jong-hun Lee, Jae-un Park, Si-hoon Song, Myung-sun Kim
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Patent number: 10331455Abstract: An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.Type: GrantFiled: July 19, 2017Date of Patent: June 25, 2019Assignee: Samsung Electronics Co., LtdInventors: Jong-hun Lee, Jae-un Park, Si-hoon Song, Myung-sun Kim
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Patent number: 10185565Abstract: Provided are a method and an apparatus for controlling a register of a reconfigurable processor. The power of a register may be efficiently used by obtaining a command for each of a plurality of read ports of the register from a memory, obtaining activation information for each of the plurality of read ports from the obtained command, and determining an address value of each of the plurality of read ports on the basis of the obtained activation information.Type: GrantFiled: November 28, 2014Date of Patent: January 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-un Park, Tai-song Jin, Do-hyung Kim, Suk-jin Kim
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Publication number: 20180101357Abstract: A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.Type: ApplicationFiled: October 6, 2017Publication date: April 12, 2018Inventors: Jae-un PARK, Jong-hun LEE, Ki-seok KWON, Dong-kwan SUH, Kang-jin YOON, Jung-uk CHO
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Publication number: 20180081692Abstract: An electronic apparatus generating compiled data used in a very long instruction word (VLIW) processor including a plurality of function units is provided. The electronic apparatus includes a storage and a processor configured to control the storage to store the compiled data in which a plurality of VLIW instructions are compiled, identify a VLIW instruction from the compiled data; and update, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within a cycle corresponding to a latency of the identified VLIW instruction and if an end cycle of another VLIW instruction is within the cycle corresponding to the latency of the identified VLIW instruction, the compiled data by including information on a cycle difference between an end cycle of the identified VLIW instruction and the end cycle of the another VLIW instruction in the multi-cycle nop instruction.Type: ApplicationFiled: July 19, 2017Publication date: March 22, 2018Inventors: Jong-hun LEE, Jae-un PARK, Si-hoon SONG, Myung-sun KIM
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Patent number: 9804853Abstract: Provided are an instruction compression apparatus and method for a very long instruction word (VLIW) processor, and an instruction fetching apparatus and method. The instruction compression apparatus includes: an indicator generator configured to generate an indicator code that indicates an issue width of an instruction bundle to be executed in the VLIW processor, and a number of No-Operation (NOP) instruction bundles following the instruction bundle; an instruction compressor configured to compress the instruction bundle by removing at least one of NOP instructions from the instruction bundle and the NOP instruction bundles following the instruction bundle; and an instruction converter configured to include the generated indicator code in the compressed instruction bundle.Type: GrantFiled: April 22, 2014Date of Patent: October 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Un Park, Suk-jin Kim
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Patent number: 9747224Abstract: Provided is a method of managing a register port, the method including performing scheduling on register ports that are used during a plurality of cycles to enable performing of a calculation; encoding data of the register ports according to results of the scheduling, the encoding of the data including, with respect to data of one of the register ports that does not have a schedule during one of the plurality of cycles, equally encoding the data of the one register port during the one cycle with data of an adjacent cycle of the one register port, the adjacent cycle being adjacent to the one cycle; and transmitting results of the encoding to a device that includes the register ports.Type: GrantFiled: March 11, 2015Date of Patent: August 29, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tai-Song Jin, Jae-Un Park, Do-hyung Kim, Seung-won Lee
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Patent number: 9639357Abstract: A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction.Type: GrantFiled: November 30, 2012Date of Patent: May 2, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Seok Kwon, Jae-Un Park, Suk-Jin Kim
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Publication number: 20160321073Abstract: Provided are a method and an apparatus for controlling a register of a reconfigurable processor. The power of a register may be efficiently used by Obtaining a command for each of a plurality of read ports of the register from a memory, obtaining activation information for each of the plurality of read ports from the obtained command, and determining an address value of each of the plurality of read ports on the basis of the obtained activation information.Type: ApplicationFiled: November 28, 2014Publication date: November 3, 2016Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-un PARK, Tai-song JIN, Do-hyung KIM, Suk-jin KIM
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Patent number: 9330057Abstract: A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.Type: GrantFiled: December 11, 2012Date of Patent: May 3, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Kwan Suh, Suk-Jin Kim, Hyeong-Seok Yu, Ki-Seok Kwon, Jae-Un Park
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Patent number: 9244883Abstract: A technology for controlling a reconfigurable processor is provided. The reconfigurable processor dynamically loads configuration data from a peripheral memory to a configuration memory while a program is being executed, in place of loading all compiled configuration data in advance into the configuration memory when booting commences. Accordingly, a reduction in capacity of a configuration memory may be achieved.Type: GrantFiled: March 2, 2010Date of Patent: January 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-un Park, Ki-seok Kwon, Sang-suk Lee
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Publication number: 20150261695Abstract: Provided is a method of managing a register port, the method including performing scheduling on register ports that are used during a plurality of cycles to enable performing of a calculation; encoding data of the register ports according to results of the scheduling, the encoding of the data including, with respect to data of one of the register ports that does not have a schedule during one of the plurality of cycles, equally encoding the data of the one register port during the one cycle with data of an adjacent cycle of the one register port, the adjacent cycle being adjacent to the one cycle; and transmitting results of the encoding to a device that includes the register ports.Type: ApplicationFiled: March 11, 2015Publication date: September 17, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tai-Song JIN, Jae-Un PARK, Do-hyung KIM, Seung-won LEE
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Patent number: 9122565Abstract: Provided is a memory controller that manages memory access requests between the processor and the memory. In response to the memory controller receiving two or more memory access requests for the same area of memory, the memory controller is configured to stall the memory controller and sequentially process the memory access requests.Type: GrantFiled: December 10, 2012Date of Patent: September 1, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Un Park, Ki-Seok Kwon, Suk-Jin Kim
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Publication number: 20150154026Abstract: In a method to execute instructions, at least one instruction executed in a predetermined cycle is acquired based on information included in each of a plurality of instructions, and a code included in the at least one instruction acquired. An instruction is allocated to at least one slot based on the analysis result, and a slot necessary to execute the instruction is selectively used. Accordingly, power consumption of a device using the method may be reduced.Type: ApplicationFiled: November 26, 2014Publication date: June 4, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-un PARK, Suk-jin Kim, Do-hyung Kim