Patents by Inventor Jae Uoon KIM

Jae Uoon KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230268356
    Abstract: A method of manufacturing a display device in a chamber in which a material including yttrium is coated on an inner surface includes: forming a first layer pattern by dry etching on a substrate; depositing a second layer material on the first layer pattern; forming a photoresist pattern on the second layer material; completing a second layer pattern by using the photoresist pattern as an etch mask; and performing an additional acid etching process by using an etching solution including at least one of hydrochloric acid, sulfuric acid, or nitric acid before the forming of the photoresist pattern on the second layer material after the dry etching to form the first layer pattern.
    Type: Application
    Filed: January 18, 2023
    Publication date: August 24, 2023
    Inventors: Yong-Hwan RYU, Woo Jin CHO, Jong-Hyun CHOUNG, Jae Uoon KIM, Sun-Jin SONG, Hyun Duck CHO
  • Patent number: 11652111
    Abstract: A display device includes a data conductive layer disposed on a substrate, a passivation layer disposed on the data conductive layer, a via layer disposed on the passivation layer, and a pixel electrode disposed on the via layer. The data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, a first data capping layer disposed on the data main metal layer, a second data capping layer disposed on the first data capping layer, and a third data capping layer disposed on the second data capping layer. The passivation layer and the via layer include a pad opening which exposes a portion of the data conductive layer in the pad area. The third data capping layer has a higher etch rate than the first and second data capping layers for a same etchant.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jong Hyun Choung, Jae Uoon Kim, Hyun Ah Sung
  • Publication number: 20230116992
    Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Applicant: Samsung Display Co., LTD.
    Inventors: Jae Uoon KIM, Hong Sick PARK, Jong Hyun CHOUNG
  • Patent number: 11594561
    Abstract: A method of manufacturing a display device in a chamber in which a material including yttrium is coated on an inner surface includes: forming a first layer pattern by dry etching on a substrate; depositing a second layer material on the first layer pattern; forming a photoresist pattern on the second layer material; completing a second layer pattern by using the photoresist pattern as an etch mask; and performing an additional acid etching process by using an etching solution including at least one of hydrochloric acid, sulfuric acid, or nitric acid before the forming of the photoresist pattern on the second layer material after the dry etching to form the first layer pattern.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: February 28, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong-Hwan Ryu, Woo Jin Cho, Jong-Hyun Choung, Jae Uoon Kim, Sun-Jin Song, Hyun Duck Cho
  • Patent number: 11557614
    Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Uoon Kim, Hong Sick Park, Jong Hyun Choung
  • Patent number: 11424312
    Abstract: A device includes a substrate including a display area and a pad area; a first conductive layer on the substrate; and a first insulating film on the first conductive layer, the first insulating film having a first contact hole in the display area to expose the first conductive layer and a pad opening exposing the first conductive layer in the pad area, the first conductive layer being arranged such that in a first region covered by the first insulating film, a second conductive capping layer of the first conductive layer is entirely on a first conductive capping layer of the first conductive layer; in a second region overlapping the contact hole, the second conductive capping layer is entirely on the first conductive capping layer; and in a third region exposed by the pad opening, the second conductive capping layer exposes at least a portion of the first conductive capping layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: August 23, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gyung Min Baek, Ju Hyun Lee, Jae Uoon Kim, Hong Sick Park, Hyun Eok Shin
  • Publication number: 20220157856
    Abstract: A display device includes a data conductive layer disposed on a substrate, a passivation layer disposed on the data conductive layer, a via layer disposed on the passivation layer, and a pixel electrode disposed on the via layer. The data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, a first data capping layer disposed on the data main metal layer, a second data capping layer disposed on the first data capping layer, and a third data capping layer disposed on the second data capping layer. The passivation layer and the via layer include a pad opening which exposes a portion of the data conductive layer in the pad area. The third data capping layer has a higher etch rate than the first and second data capping layers for a same etchant.
    Type: Application
    Filed: August 31, 2021
    Publication date: May 19, 2022
    Applicant: Samsung Display Co., LTD.
    Inventors: Jong Hyun CHOUNG, Jae Uoon KIM, Hyun Ah SUNG
  • Publication number: 20210327927
    Abstract: A method of manufacturing a display device in a chamber in which a material including yttrium is coated on an inner surface includes: forming a first layer pattern by dry etching on a substrate; depositing a second layer material on the first layer pattern; forming a photoresist pattern on the second layer material; completing a second layer pattern by using the photoresist pattern as an etch mask; and performing an additional acid etching process by using an etching solution including at least one of hydrochloric acid, sulfuric acid, or nitric acid before the forming of the photoresist pattern on the second layer material after the dry etching to form the first layer pattern.
    Type: Application
    Filed: October 20, 2020
    Publication date: October 21, 2021
    Inventors: YONG-HWAN RYU, Woo Jin Cho, Jong-Hyun Choung, Jae Uoon Kim, Sun-Jin Song, Hyun Duck Cho
  • Publication number: 20210249451
    Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.
    Type: Application
    Filed: August 26, 2020
    Publication date: August 12, 2021
    Applicant: Samsung Display Co., LTD.
    Inventors: Jae Uoon KIM, Hong Sick PARK, Jong Hyun CHOUNG
  • Publication number: 20210091161
    Abstract: A device includes a substrate including a display area and a pad area; a first conductive layer on the substrate; and a first insulating film on the first conductive layer, the first insulating film having a first contact hole in the display area to expose the first conductive layer and a pad opening exposing the first conductive layer in the pad area, the first conductive layer being arranged such that in a first region covered by the first insulating film, a second conductive capping layer of the first conductive layer is entirely on a first conductive capping layer of the first conductive layer; in a second region overlapping the contact hole, the second conductive capping layer is entirely on the first conductive capping layer; and in a third region exposed by the pad opening, the second conductive capping layer exposes at least a portion of the first conductive capping layer.
    Type: Application
    Filed: May 12, 2020
    Publication date: March 25, 2021
    Inventors: Gyung Min BAEK, Ju Hyun LEE, Jae Uoon KIM, Hong Sick PARK, Hyun Eok SHIN
  • Patent number: 10825844
    Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 3, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Hyun Choung, Jae Uoon Kim
  • Publication number: 20200243563
    Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.
    Type: Application
    Filed: May 28, 2019
    Publication date: July 30, 2020
    Inventors: Jong Hyun Choung, Jae Uoon KIM