Patents by Inventor Jae-Won Cha
Jae-Won Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170220413Abstract: A semiconductor memory device may include: a memory cell array comprising: a Content Addressable Memory (CAM) cell block including CAM cells storing option Information including operation setting information for controlling an operation of the semiconductor memory device, and error check information for the operation setting information; and memory blocks including memory cells for storing data; an error detection unit suitable for reading out, in response to a CAM read command, the operation setting information and the error check information stored in the CAM cell block and outputting an error detection signal indicating whether there is an error; and a control logic suitable for determining and outputting a state of a ready/busy signal depending on the error detection signal.Type: ApplicationFiled: June 6, 2016Publication date: August 3, 2017Inventors: Jae-Won CHA, Jae-Woo PARK
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Patent number: 9613717Abstract: An error correction circuit includes: a failure detection unit suitable for detecting failed data among a plurality of data; a data output control unit suitable for selectively outputting test data corresponding to a predetermined amount of data excluding the failed data; and an error correction unit suitable for performing a unit ECC operation on the test data.Type: GrantFiled: September 15, 2015Date of Patent: April 4, 2017Assignee: SK Hynix Inc.Inventors: Jae-Won Cha, Jae-Woo Park
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Publication number: 20160314041Abstract: An error correction circuit includes: a failure detection unit suitable for detecting failed data among a plurality of data; a data output control unit suitable for selectively outputting test data corresponding to a predetermined amount of data excluding the failed data; and an error correction unit suitable for performing a unit ECC operation on the test data.Type: ApplicationFiled: September 15, 2015Publication date: October 27, 2016Inventors: Jae-Won CHA, Jae-Woo PARK
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Patent number: 8812777Abstract: A nonvolatile memory device includes: N (N is an integer equal to or greater than 2) number of nonvolatile memory cells disposed in a flag area of a page, N number of flag page buffers configured to input and output flag data to and from the nonvolatile memory cells of the flag area, and a data input/output control unit configured to select R number of flag page buffers so that the flag data is inputted and outputted from the R selected flag page buffers and no flag data is inputted and outputted through unselected N-R number of flag page buffers, wherein no one flag page buffer of the R selected flag page buffers is immediately adjacent to another one of the R selected flag page buffers.Type: GrantFiled: June 5, 2012Date of Patent: August 19, 2014Assignee: Hynix Semiconductor Inc.Inventors: Jae-Won Cha, Sung-Hoon Ahn
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Publication number: 20130151758Abstract: A nonvolatile memory device includes: N (N is an integer equal to or greater than 2) number of nonvolatile memory cells disposed in a flag area of a page, N number of flag page buffers configured to input and output flag data to and from the nonvolatile memory cells of the flag area, and a data input/output control unit configured to select R number of flag page buffers so that the flag data is inputted and outputted from the R selected flag page buffers and no flag data is inputted and outputted through unselected N?R number of flag page buffers, wherein no one flag page buffer of the R selected flag page buffers is immediately adjacent to another one of the R selected flag page buffers.Type: ApplicationFiled: June 5, 2012Publication date: June 13, 2013Inventors: Jae-Won CHA, Sung-Hoon AHN
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Patent number: 7948805Abstract: A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.Type: GrantFiled: October 11, 2010Date of Patent: May 24, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sam-Kyu Won, Jae-Won Cha, Kwang-Ho Baek
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Patent number: 7813188Abstract: A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator cell. A first verifying operation is performed based on a first verifying voltage of the main cell and the indicator cell. The program operation and the first verifying operation are performed repeatedly until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage. A second verifying operation is performed on the main cell based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.Type: GrantFiled: January 25, 2008Date of Patent: October 12, 2010Assignee: Hynix Semiconductor Inc.Inventors: Sam-Kyu Won, Jae-Won Cha, Kwang-Ho Baek
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Patent number: 7623403Abstract: A NAND flash memory device having memory cells for storing data includes a fuse circuit configured to store option information for operation of the NAND flash memory device as logic codes. A register circuit includes registers for temporarily storing the logic codes stored in the fuse circuit. A test circuit is configured to change the logic code stored in the register circuit and store the changed logic code irrespective of the logic code of the fuse circuit for test operation of the NAND flash memory device. A processor is configured to control operation of the NAND flash memory device.Type: GrantFiled: December 3, 2007Date of Patent: November 24, 2009Assignee: Hynix Semiconductor Inc.Inventors: Jae-Won Cha, Sam-Kyu Won, Kwang-Ho Baek
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Patent number: 7243994Abstract: Disclosed herein is a continuously operable seat-reclining device having an improved actuator to substantially carry out a reclining operation of the reclining device such that an actuating force of a shaft is uniformly transmitted to the entirety of a coupling. The continuously operable seat-reclining device basically comprises an upper teeth bracket and a lower teeth bracket securely fixed to a seat back frame and a cushion frame, respectively, the upper teeth bracket being provided with upper teeth, the lower teeth bracket being provided with lower teeth, the upper teeth of the upper teeth bracket being engaged with the lower teeth of the lower teeth bracket, a cam hole formed at the center of the lower teeth bracket, and an actuator disposed between the cam hole and the cam-maintaining ring for moving the upper teeth bracket relative to the lower teeth bracket.Type: GrantFiled: November 12, 2004Date of Patent: July 17, 2007Assignee: DAS Co., Ltd.Inventor: Jae-Won Cha
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Patent number: 7195318Abstract: A reclining device of a vehicle seat for easily locking and releasing the vehicle seat so as to increase performance of the vehicle seat and to improve quality thereof. The reclining device is easily assembled, by removing minor shortcomings that may occur during the assembly process, and enhances engagement of the locking teeth with the upper teeth when the reclining device is installed to a vehicle, so that the convenience as well as quality, strength, and durability of the reclining device are enhanced.Type: GrantFiled: November 1, 2004Date of Patent: March 27, 2007Assignee: DAS Co., Ltd.Inventors: Jae-Won Cha, Myung-Jin Chang
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Publication number: 20060091713Abstract: A reclining device of a vehicle seat for easily locking and releasing the vehicle seat so as to increase performance of the vehicle seat and to improve quality thereof. The reclining device is easily assembled, by removing minor shortcomings that may occur during the assembly process, and enhances engagement of the locking teeth with the upper teeth when the reclining device is installed to a vehicle, so that the convenience as well as quality, strength, and durability of the reclining device are enhanced.Type: ApplicationFiled: November 1, 2004Publication date: May 4, 2006Inventors: Jae-Won Cha, Myung-Jin Chang
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Publication number: 20050110322Abstract: Disclosed herein is a continuously operable seat-reclining device having an improved actuator to substantially carry out a reclining operation of the reclining device such that an actuating force of a shaft is uniformly transmitted to the entirety of a coupling. The continuously operable seat-reclining device basically comprises an upper teeth bracket and a lower teeth bracket securely fixed to a seat back frame and a cushion frame, respectively, the upper teeth bracket being provided with upper teeth, the lower teeth bracket being provided with lower teeth, the upper teeth of the upper teeth bracket being engaged with the lower teeth of the lower teeth bracket, a cam hole formed at the center of the lower teeth bracket, and an actuator disposed between the cam hole and the cam-maintaining ring for moving the upper teeth bracket relative to the lower teeth bracket.Type: ApplicationFiled: November 12, 2004Publication date: May 26, 2005Inventor: Jae-Won Cha