Patents by Inventor Jae Won Nam
Jae Won Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8264268Abstract: Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.Type: GrantFiled: July 26, 2010Date of Patent: September 11, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Patent number: 8164504Abstract: A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2V-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.Type: GrantFiled: September 15, 2010Date of Patent: April 24, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Patent number: 8164497Abstract: Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.Type: GrantFiled: May 11, 2010Date of Patent: April 24, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Jae Won Nam, Young Deuk Jeon, Young Kyun Cho, Jong Kee Kwon
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Patent number: 8058863Abstract: A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about ½, thereby miniaturizing the band-gap reference voltage generator. A reference voltage lower than or equal to 1 V can be provided by resistors respectively connected to the bipolar transistors in parallel.Type: GrantFiled: April 22, 2009Date of Patent: November 15, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, JongKee Kwon
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Patent number: 8059022Abstract: A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized.Type: GrantFiled: May 4, 2010Date of Patent: November 15, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Publication number: 20110227774Abstract: A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2?-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.Type: ApplicationFiled: September 15, 2010Publication date: September 22, 2011Applicant: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Patent number: 7999719Abstract: A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.Type: GrantFiled: April 30, 2009Date of Patent: August 16, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Young Deuk Jeon, Young Kyun Cho, Jae Won Nam, Jong Kee Kwon
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Patent number: 7978117Abstract: A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.Type: GrantFiled: August 11, 2009Date of Patent: July 12, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Young Deuk Jeon, Young Kyun Cho, Jae Won Nam, Jong Kee Kwon
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Patent number: 7977979Abstract: A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).Type: GrantFiled: July 22, 2009Date of Patent: July 12, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Publication number: 20110102220Abstract: Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.Type: ApplicationFiled: May 11, 2010Publication date: May 5, 2011Applicant: Electronics and Telecommunications Research InstituteInventors: Jae Won NAM, Young Deuk Jeon, Young Kyun Cho, Jong Kee Kwon
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Patent number: 7893860Abstract: A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.Type: GrantFiled: May 27, 2009Date of Patent: February 22, 2011Assignee: Electronic and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Publication number: 20110032134Abstract: A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized.Type: ApplicationFiled: May 4, 2010Publication date: February 10, 2011Applicant: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Publication number: 20110018629Abstract: A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground.Type: ApplicationFiled: July 9, 2010Publication date: January 27, 2011Applicant: Electronics and Telecommunications Research InstituteInventors: Young Deuk JEON, Young Kyun Cho, Jae Won Nam, Jong Kee Kwon
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Publication number: 20110018605Abstract: Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.Type: ApplicationFiled: July 26, 2010Publication date: January 27, 2011Applicant: Electronics and Telecommunications Research InstituteInventors: Young Kyun CHO, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Patent number: 7847713Abstract: Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution.Type: GrantFiled: April 30, 2009Date of Patent: December 7, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Jae Won Nam, Young Deuk Jeon, Young Kyun Cho, Jong Kee Kwon
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Publication number: 20100156469Abstract: A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).Type: ApplicationFiled: July 22, 2009Publication date: June 24, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Publication number: 20100156692Abstract: A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.Type: ApplicationFiled: August 11, 2009Publication date: June 24, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Young Deuk JEON, Young Kyun Cho, Jae Won Nam, Jong Kee Kwon
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Publication number: 20100158277Abstract: Provided is a read-out circuit that is connected to a microphone and configured to linearly amplify a current signal generated by the microphone and output the amplified current signal. The read-out circuit includes an amplification unit and a feedback resistor. The amplification unit has an amplification gain between 0 and 1. The feedback resistor is connected between input and output terminals of the amplification unit. As the amplification gain of the amplification unit becomes closer to 1, an input impedance becomes higher. A preamp of the read-out circuit can have a high input impedance due to the amplification gain, and the read-out circuit can be manufactured using a CMOS process.Type: ApplicationFiled: July 29, 2009Publication date: June 24, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Min Hyung CHO, Yi Gyeong Kim, Jae Won Nam, Jong Kee Kwon
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Publication number: 20100123611Abstract: A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.Type: ApplicationFiled: May 27, 2009Publication date: May 20, 2010Applicant: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Jae Won Nam, Jong Kee Kwon
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Patent number: 7705764Abstract: Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit.Type: GrantFiled: August 26, 2008Date of Patent: April 27, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Seung Chul Lee, Jae Won Nam, Young Deuk Jeon, Jong Kee Kwon