Abstract: An electronic device includes a display unit including an active area configured to display an image, a peripheral area adjacent to the active area, and an input sensing unit disposed on the display unit within the active area. The input sensing unit includes a first sensing electrode disposed in the active area and a second sensing electrode spaced apart from the first sensing electrode and disposed in the active area.

Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

Abstract: A system, method, and apparatus for generating a normalization of a single two-dimensional image of an unconstrained human face. The system receives the single two-dimensional image of the unconstrained human face, generates an undistorted face based on the unconstrained human face by removing perspective distortion from the unconstrained human face via a perspective undistortion network, generates an evenly lit face based on the undistorted face by normalizing lighting of the undistorted face via a lighting translation network, and generates a frontalized and neutralized expression face based on the evenly lit face via an expression neutralization network.

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

Abstract: A server may include a communication circuit and at least one processor. The at least one processor may be connected to a first electronic device and a second electronic device, using the communication circuit, and may be configured to: obtain first call log information including at least one outgoing call made using a call function of the first electronic device by the second electronic device, determine whether the second electronic device satisfies a first condition for determining that the second electronic device is a spam caller, based on the first call log information, search for one or more external electronic devices located around the second electronic device, based on the first condition being satisfied, obtain second call log information about the one or more external electronic devices, and determine at least one of the one or more external electronic devices or the second electronic device as a spam caller, based on the second call log information.

Abstract: A system and method for generating a digital avatar from a two-dimensional input image in accordance with a machine learning models is provided. The machine learning models are generative adversarial networks trained to process a latent code into three-dimensional data and color data. A generative adversarial network (GAN) inversion optimization algorithm is run on the first machine learning model to map the input image to a latent code for the first machine learning model. The latent code is used to generate unstructured 3D data and color information. A GAN inversion optimization algorithm is then run on the second machine learning model to determine a latent code for the second machine learning model, based at least on the output of the first machine learning model. The latent code for the second machine learning model is then used to generate the data for the digital avatar.

Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.

Abstract: According to an embodiment of the disclosure, an electronic device is provided. The electronic device includes a communication module and at least one processor connected to the communication module. The at least one processor is configured to configure a call setup with an external electronic device through the communication module. The at least one processor is configured to control the communication module to transmit at least one request message based on a first protocol through the communication module, and receive at least one response message corresponding to the request message. The at least one processor is configured to control the communication module to transmit a howling generation sound source through the communication module, and receive a howling response corresponding to the howling generation sound source. The at least one processor is configured to determine whether a call between the electronic device and the external electronic device is a normal call.

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

Abstract: In examples, locations of facial landmarks may be applied to one or more machine learning models (MLMs) to generate output data indicating profiles corresponding to facial expressions, such as facial action coding system (FACS) values. The output data may be used to determine geometry of a model. For example, video frames depicting one or more faces may be analyzed to determine the locations. The facial landmarks may be normalized, then be applied to the MLM(s) to infer the profile(s), which may then be used to animate the mode for expression retargeting from the video. The MLM(s) may include sub-networks that each analyze a set of input data corresponding to a region of the face to determine profiles that correspond to the region. The profiles from the sub-networks, along global locations of facial landmarks may be used by a subsequent network to infer the profiles for the overall face.

Abstract: An integrated circuit including a plurality of stacked metal layers and a method of manufacturing the integrated circuit are provided. The method includes: providing a plurality of standard cells, each of which includes cell patterns respectively formed on the plurality of metal layers; and forming, on a particular metal layer among the plurality of metal layers which includes patterns extending in a first direction that are respectively formed on a plurality of tracks that are spaced apart from each other in a second direction, an additional pattern between adjacent patterns formed on a particular track of the plurality of tracks based on an interval between the adjacent patterns exceeding a reference value.

Abstract: An electronic device is disclosed. An electronic device according to various embodiments comprises: a processor; and a memory electrically connected to the processor, wherein the processor may be configured to: obtain a plurality of first parameters associated with attributes of at least one malicious code and a plurality of second parameters associated with a system in which the at least one malicious code is executed; obtain a similarity on the basis of a first comparison result according to a first comparison method between the plurality of first parameters and a second comparison result according to a second comparison method between the plurality of second parameters; and classify the at least one malicious code into at least one cluster on the basis of the similarity between the at least one malicious code. Other various embodiments may be provided.

Abstract: Provided is an integrated circuit including standard cells arranged over a plurality of rows. The standard cells may include: a plurality of functional cells each implemented as a logic circuit; and a plurality of filler cells including at least one first filler cell and at least one second filler cell that each include at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and wherein the at least one first filler cell and the at least one second filler cell have a same size as each other, and a density of one of the at least one pattern of the at least one first filler cell is different from a density of one of the at least one pattern of the at least one second filler cell.

Abstract: Apparatuses, systems, and techniques are presented to generate media content.

Abstract: Disclosed is a terminal device.

Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

Abstract: An integrated circuit includes a first cell including a first lower pattern extending in a first direction along a first track in a first wiring layer; and a second cell including a second lower pattern that extends in the first direction along the first track in the first wiring layer, and is a minimum space of the first wiring layer or farther apart from the first lower pattern, wherein the first lower pattern corresponds to a pin of the first cell, and the second lower pattern is farther apart from a boundary between the first cell and the second cell than the first lower pattern is.

Abstract: An integrated circuit including a first standard cell placed continuously on a row having a first height and a row having a second height different from the first height. The integrated circuit also includes a second standard cell continuously placed on a row having the first height and a row having the second height, a plurality of first power lines formed on boundaries of the plurality of rows and configured to supply a first supply voltage to the standard cells, and a plurality of second power lines formed on boundaries of the plurality of rows and configured to supply a second supply voltage to the standard cells. A placement sequence of the power lines supplying a voltage to the first standard cell being different from a placement sequence of the power lines supplying a voltage to the second standard cell.

Abstract: An integrated circuit (IC) includes: a plurality of gate electrodes extending in a first direction and arranged in a second direction that is orthogonal to the first direction; a plurality of first power lines extending in the first direction to supply power to the standard cell, and respectively placed to be adjacent to first sides of the gate electrodes; and a plurality of signal lines extending in the first direction to transfer an input signal or an output signal of the standard cell, and respectively placed to be adjacent to second sides of the gate electrodes.

Abstract: A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row