Patents by Inventor Jae-Woong Choi

Jae-Woong Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12336098
    Abstract: A printed circuit board includes a wiring board including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers, a first die embedded in the plurality of insulating layers, a bridge embedded on the first die in the plurality of insulating layers, a second die mounted on the wiring board, and a third die mounted on the wiring board.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: June 17, 2025
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Woong Choi, Jae Ho Shin, Joo Hwan Jung
  • Publication number: 20250174059
    Abstract: In a method and apparatus for controlling a vehicle, the vehicle control apparatus includes rear-wheels steering unit configured to steer a rear wheel, to measure a rear wheel angle, and generate a status signal, a failure determination unit operatively connected to the rear-wheel steering unit and configured to determine a failure situation of the rear-wheel steering unit based on the status signal, a curvature prediction unit configured to generate a predicted curvature of a traveling route of a vehicle based on the failure situation, and a position prediction unit operatively connected to the curvature prediction unit and configured to generate a predicted position of the vehicle based on the predicted curvature, wherein the curvature prediction unit generates the predicted curvature based on the rear wheel angle.
    Type: Application
    Filed: November 12, 2024
    Publication date: May 29, 2025
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Jeong Min CHO, Jae Woong CHOI
  • Publication number: 20250174058
    Abstract: In a method and an apparatus for controlling vehicle, the vehicle control apparatus includes a rear wheel steering unit configured to steer rear wheels, measure a rear wheel angle, and generate a status signal, a failure determination unit configured to determine a failure situation of the rear wheel steering unit based on the status signal and a curvature prediction unit configured to generate a predicted curvature of a traveling route of a vehicle based on the failure situation, wherein, the curvature prediction unit generates the predicted curvature based on the rear wheel angle.
    Type: Application
    Filed: November 12, 2024
    Publication date: May 29, 2025
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Jeong Min CHO, Jae Woong CHOI
  • Publication number: 20250158085
    Abstract: A method of manufacturing a Ti material for a fuel cell separator includes rolling a Ti raw material of a pure Ti material or a Ti alloy material, deposition coating Ti ion particles on the Ti raw material by physical vapor deposition (PVD), and oxidation heat treating to form a conductive oxide layer of a TiO2-x(0<x<1) structure around the Ti ion particles deposited by the deposition coating. According to the present disclosure, the Ti material can be used to achieve both corrosion resistance and conductivity.
    Type: Application
    Filed: March 20, 2024
    Publication date: May 15, 2025
    Inventors: Dong-Jae Choi, Jae-Woong Choi
  • Patent number: 12294536
    Abstract: Disclosed is a method of obfuscating a Controller Area Network (CAN) message performed by a first computing device including a processor, the method including: obtaining a first index from a first input value corresponding to a first time point by using an index output algorithm; determining a first CAN ID of the first computing device corresponding to the first index based on a predetermined CAN ID table; and generating a first normal CAN message including the first CAN ID and first normal data.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: May 6, 2025
    Assignee: Korea University Research and Business Foundation
    Inventors: Huy Kang Kim, Hwejae Lee, Sangho Lee, Yeon Jae Kang, Daekwon Pi, Jae Woong Choi, Huiju Lee
  • Publication number: 20250126718
    Abstract: A printed circuit board includes a first substrate including a first antenna pattern; a second substrate disposed on a first substrate and including a second antenna pattern; a metal layer disposed between the first and second substrates; and a bonding layer disposed between the first and second substrates. At least one of the first and second substrates has a cavity having at least a portion disposed between the first and second antenna patterns, each of the first and second substrates includes an organic material, and the bonding layer includes an inorganic material.
    Type: Application
    Filed: June 12, 2024
    Publication date: April 17, 2025
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Ho SHIN, Jae Woong CHOI
  • Patent number: 12279364
    Abstract: The present disclosure relates to a printed circuit board. The printed circuit board includes a plurality of insulating layers each having a plurality of concave portions; a plurality of conductor pattern layers disposed in a plurality of concave portions of each of the plurality of insulating layers; first and second via holes connected to one of the plurality of concave portions independently of each other and penetrating through at least two of the plurality of insulating layers independently of each other; and first and second via conductors disposed in the first and second via holes, respectively, and connecting two of the plurality of conductor pattern layers independently of each other. An average width of the first via conductor is greater than that of the second via conductor on a cross-section.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: April 15, 2025
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Woong Choi, Jae Ho Shin
  • Patent number: 12250766
    Abstract: An antenna module includes a wiring structure including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; an antenna disposed on an upper surface of the wiring structure; a heat dissipation structure disposed around the antenna on the upper surface of the wiring structure; and an encapsulant disposed on the upper surface of the wiring structure and covering at least a portion of each of the antenna and the heat dissipation structure.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: March 11, 2025
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Woong Choi, Jin Won Lee
  • Patent number: 12218155
    Abstract: A semiconductor device with multiple zero differential transconductance includes: a conductive substrate; a first insulating layer and a second insulating layer disposed on the conductive substrate; a first semiconductor and a second semiconductor disposed on first portions of the first insulating layer and the second insulating layer, respectively; a first buffer layer and a second buffer layer disposed on electrode contact areas of the first semiconductor and the second semiconductor, respectively; and an anode electrode and a cathode electrode disposed on second portions, which are different from the first portions, of the first insulating layer and the second insulating layer and on the first buffer layer and the second buffer layer, respectively, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: February 4, 2025
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Jae Woong Choi, Je Jun Lee, Ju Hee Lee
  • Patent number: 12206420
    Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: January 21, 2025
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yi-Gyeong Kim, Young-Su Kwon, Su-Jin Park, Young-Deuk Jeon, Min-Hyung Cho, Jae-Woong Choi
  • Publication number: 20240195399
    Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
    Type: Application
    Filed: July 18, 2023
    Publication date: June 13, 2024
    Inventors: Yi-Gyeong KIM, Young-Su KWON, Su-Jin PARK, Young-Deuk JEON, Min-Hyung CHO, Jae-Woong CHOI
  • Publication number: 20240194241
    Abstract: Disclosed herein is an apparatus for adjusting a reference voltage. The apparatus may include a gate signal generation unit for generating an RDQS gate signal, a reference voltage generation unit for setting a reference voltage based on the RDQS gate signal, and a reset counter for holding a voltage at the time at which the RDQS gate signal becomes low when the RDQS gate signal is not applied to the reference voltage generation unit for a specific time period.
    Type: Application
    Filed: July 18, 2023
    Publication date: June 13, 2024
    Inventors: Young-Deuk JEON, Young-Su KWON, Yi-Gyeong KIM, Su-Jin PARK, Min-Hyung CHO, Jae-Woong CHOI
  • Publication number: 20240179830
    Abstract: The present disclosure relates to a printed circuit board. The printed circuit board includes a plurality of insulating layers each having a plurality of concave portions; a plurality of conductor pattern layers disposed in a plurality of concave portions of each of the plurality of insulating layers; first and second via holes connected to one of the plurality of concave portions independently of each other and penetrating through at least two of the plurality of insulating layers independently of each other; and first and second via conductors disposed in the first and second via holes, respectively, and connecting two of the plurality of conductor pattern layers independently of each other. An average width of the first via conductor is greater than that of the second via conductor on a cross-section.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 30, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Woong Choi, Jae Ho Shin
  • Publication number: 20240163139
    Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Young-deuk JEON, Young-Su KWON, Yi-Gyeong KIM, Su-Jin PARK, Min-Hyung CHO, Jae-Woong CHOI
  • Patent number: 11963311
    Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers and having a cavity penetrating through a portion of the plurality of insulating layers, a passive component disposed in the cavity and including an external electrode electrically connected to at least one of the plurality of wiring layers, and a bridge disposed on the passive component in the cavity and including one or more circuit layers electrically connected to the external electrode.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Woong Choi, Yun Je Ji, Seung Eun Lee, Yong Hoon Kim
  • Publication number: 20240097841
    Abstract: Disclosed is a method of obfuscating a Controller Area Network (CAN) message performed by a first computing device including a processor, the method including: obtaining a first index from a first input value corresponding to a first time point by using an index output algorithm; determining a first CAN ID of the first computing device corresponding to the first index based on a predetermined CAN ID table; and generating a first normal CAN message including the first CAN ID and first normal data.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Huy Kang KIM, Hwejae LEE, Sangho LEE, Yeon Jae KANG, Daekwon PI, Jae Woong CHOI, Huiju LEE
  • Patent number: 11921158
    Abstract: Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: March 5, 2024
    Inventors: Byung-Sung Kim, Yun-Hyok Choi, Gyuyeol Kim, Sungjung Kim, Cheol-Heui Park, Sanghoon Lee, Jae-Woong Choi
  • Publication number: 20240039931
    Abstract: [SUMMARY] A method of detecting a sequence-based intrusion by using a Database CAN (DBC) file, the method being performed by a computing device including a processor according to some exemplary embodiments of the present disclosure, includes: obtaining a first Controller Area Network (CAN) message generated from a CAN; determining the first CAN message as a first category among a plurality of categories based on a pre-stored DBC file; obtaining first predictive data from the first CAN message by using a pre-trained first neural network model, the pre-trained first neural network model corresponding to the first category and including a first hidden layer; and comparing the first predictive data and first actual data obtained based on the first CAN message to determine whether the first CAN message has an anomaly.
    Type: Application
    Filed: July 19, 2023
    Publication date: February 1, 2024
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Huy Kang KIM, Hwejae LEE, Sangho LEE, Yeon Jae KANG, Daekwon PI, Jae Woong CHOI, Huiju LEE
  • Publication number: 20230371173
    Abstract: An antenna module includes a wiring structure including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; an antenna disposed on an upper surface of the wiring structure; a heat dissipation structure disposed around the antenna on the upper surface of the wiring structure; and an encapsulant disposed on the upper surface of the wiring structure and covering at least a portion of each of the antenna and the heat dissipation structure.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Woong Choi, Jin Won Lee
  • Publication number: 20230333160
    Abstract: Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.
    Type: Application
    Filed: December 6, 2022
    Publication date: October 19, 2023
    Applicants: Samsung Electronics Co., Ltd., Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: BYUNG-SUNG KIM, YUN-HYOK CHOI, GYUYEOL KIM, SUNGJUNG KIM, CHEOL-HEUI PARK, SANGHOON LEE, JAE-WOONG CHOI