Patents by Inventor Jae-Woong Yu
Jae-Woong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11557523Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.Type: GrantFiled: February 5, 2021Date of Patent: January 17, 2023Assignee: SK hynix Inc.Inventors: Jae Woong Yu, So Hyun Jung
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Publication number: 20210159137Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.Type: ApplicationFiled: February 5, 2021Publication date: May 27, 2021Applicant: SK hynix Inc.Inventors: Jae Woong YU, So Hyun JUNG
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Patent number: 10950512Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.Type: GrantFiled: December 21, 2018Date of Patent: March 16, 2021Assignee: SK hynix Inc.Inventors: Jae Woong Yu, So Hyun Jung
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Patent number: 10879160Abstract: The semiconductor package includes a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines.Type: GrantFiled: December 14, 2018Date of Patent: December 29, 2020Assignee: SK hynix Inc.Inventors: Jae Woong Yu, So Hyun Jung
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Publication number: 20190237376Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.Type: ApplicationFiled: December 21, 2018Publication date: August 1, 2019Applicant: SK hynix Inc.Inventors: Jae Woong YU, So Hyun JUNG
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Publication number: 20190237397Abstract: There is provided a method of forming a semiconductor package and a semiconductor package. The semiconductor package includes a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines.Type: ApplicationFiled: December 14, 2018Publication date: August 1, 2019Applicant: SK hynix Inc.Inventors: Jae Woong YU, So Hyun JUNG
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Publication number: 20190237398Abstract: A semiconductor package includes a semiconductor chip and a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines, opening holes located between remaining portions of the second group of conductive lines to separate the second group of conductive lines from each other.Type: ApplicationFiled: December 24, 2018Publication date: August 1, 2019Applicant: SK hynix Inc.Inventors: Jae Woong YU, Ha Gyeong SONG, Jung Youn LEE
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Patent number: 9536861Abstract: A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a center portion of the substrate, and a plurality of first bond fingers, a plurality of second bond fingers, and a plurality of external electrodes arranged on the second surface; two or more first semiconductor chips each having a plurality of first bonding pads arranged adjacent to edges of the first semiconductor chips, and each of the first semiconductor chips separately attached to the first surface of the substrate in a face-down type position exposing the first bonding pads; and a second semiconductor chip having a plurality of second bonding pads arranged at a center portion of the second semiconductor chip, and attached to each of the first semiconductor chips in a face-down type position exposing the second bonding pads through the window.Type: GrantFiled: April 21, 2015Date of Patent: January 3, 2017Assignee: SK HYNIX INC.Inventors: Jae Woong Yu, Jong Seo Jung, So Hyun Jung, Seong Cheol Shin
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Publication number: 20160172331Abstract: A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a center portion of the substrate, and a plurality of first bond fingers, a plurality of second bond fingers, and a plurality of external electrodes arranged on the second surface; two or more first semiconductor chips each having a plurality of first bonding pads arranged adjacent to edges of the first semiconductor chips, and each of the first semiconductor chips separately attached to the first surface of the substrate in a face-down type position exposing the first bonding pads; and a second semiconductor chip having a plurality of second bonding pads arranged at a center portion of the second semiconductor chip, and attached to each of the first semiconductor chips in a face-down type position exposing the second bonding pads through the window.Type: ApplicationFiled: April 21, 2015Publication date: June 16, 2016Inventors: Jae Woong YU, Jong Seo JUNG, So Hyun JUNG, Seong Cheol SHIN
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Publication number: 20140361437Abstract: Package substrates are provided. The package substrate includes a core layer having a first surface defining trench portions and ridge portions between the trench portions, at least one first trace on a bottom surface of each of the trench portions, and second traces on respective ones of top surfaces of the ridge portions. Related methods are also provided.Type: ApplicationFiled: November 18, 2013Publication date: December 11, 2014Applicant: SK hynix Inc.Inventors: Hyun Chul SEO, Jong Hoon KIM, Jae Woong YU
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Patent number: 8071414Abstract: The present invention relates to a method of fabricating an organic photovoltaic device with improved power conversion efficiency by reducing lateral contribution of series resistance between subcells through active area partitioning by introducing a patterned structure of insulating partitioning walls inside the device. According to the method of the present invention, since the lateral contribution of series resistance between the partitioned subcells is minimized and each subcell works independently, there is no interference phenomenon against the current output of each subcells. As such, the function of a charge extraction layer with high conductivity can be maximized. Thus, the method of the present invention can be effectively used in the fabrication and development of a next-generation large area organic thin layer photovoltaic cell device.Type: GrantFiled: August 13, 2008Date of Patent: December 6, 2011Assignee: Korea Institute of Science and TechnologyInventors: Jae-Woong Yu, Byung Doo Chin, Jai Kyeong Kim, Nam Soo Kang
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Patent number: 7740771Abstract: Organic white-light-emitting blend materials were prepared by light-doping method and electroluminescent devices fabricated using the same, including a transparent substance, translucent electrode, white-light-emitting layer and metal electrode in order, can efficiently control Förster energy transfer in organic light-emitting materials by performing light doping, thus to fabricate a white electroluminescent device using the blend materials which can emit white-light with high efficiency. The white-light-emitting blend materials can be obtained by the light-doping method, in which the energy transfer occurs only between a host which is a donor and each dopant which is an acceptor, while the energy transfers between dopants are efficiently blocked.Type: GrantFiled: November 13, 2006Date of Patent: June 22, 2010Assignee: Korea Institute of Science and TechnologyInventors: Young-Chul Kim, Hyun-Nam Cho, Tae-Woo Lee, O-Ok Park, Jai-Kyeong Kim, Jae-Woong Yu
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Publication number: 20090133752Abstract: The present invention relates to a method of fabricating an organic photovoltaic device with improved power conversion efficiency by reducing lateral contribution of series resistance between subcells through active area partitioning by introducing a patterned structure of insulating partitioning walls inside the device. According to the method of the present invention, since the lateral contribution of series resistance between the partitioned subcells is minimized and each subcell works independently, there is no interference phenomenon against the current output of each subcells. As such, the function of a charge extraction layer with high conductivity can be maximized. Thus, the method of the present invention can be effectively used in the fabrication and development of a next-generation large area organic thin layer photovoltaic cell device.Type: ApplicationFiled: August 13, 2008Publication date: May 28, 2009Inventors: Jae-Woong Yu, Byung Doo Chin, Jai Kyeong Kim, Nam Soo Kang
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Patent number: 7242142Abstract: There is provided a polymer electroluminescent device, which comprises a transparent substrate, an anode, a polymer emitting layer, a polymer insulating nanolayer and a cathode. The polymer insulating nanolayer having the dielectric constant (?) of less than 3.0 is located between the cathode and the polymer emitting layer. According to the present invention, it is possible to obtain the polymer electroluminescent device showing more improved luminance efficiency.Type: GrantFiled: December 29, 2004Date of Patent: July 10, 2007Assignee: Korea Institute of Science and TechnologyInventors: Young Chul Kim, Jai Kyeong Kim, Jae-Woong Yu, O Ok Park, Jong Hyeok Park
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Publication number: 20070069178Abstract: Organic white-light-emitting blend materials were prepared by light-doping method and electroluminescent devices fabricated using the same, including a transparent substance, translucent electrode, white-light-emitting layer and metal electrode in order, can efficiently control Förster energy transfer in organic light-emitting materials by performing light doping, thus to fabricate a white electroluminescent device using the blend materials which can emit white-light with high efficiency. The white-light-emitting blend materials can be obtained by the light-doping method, in which the energy transfer occurs only between a host which is a donor and each dopant which is an acceptor, while the energy transfers between dopants are efficiently blocked.Type: ApplicationFiled: November 13, 2006Publication date: March 29, 2007Applicant: Korea Institute of Science and TechnologyInventors: Young Chul Kim, Hyun Nam Cho, Tae Woo Lee, O Ok Park, Jai Kyeong Kim, Jae Woong Yu
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Patent number: 6995505Abstract: A polymeric electroluminescent device suppresses photo-oxidation and enhances luminous stability and efficiency by using a nanocomposite of a luminescent polymer and metal nanoparticles as its emitting layer.Type: GrantFiled: October 31, 2003Date of Patent: February 7, 2006Assignee: Korea Institute of Science and TechnologyInventors: Young Chul Kim, Jai Kyeong Kim, Jae-Woong Yu, O Ok Park, Jong Hyeok Park, Yong Taik Lim
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Publication number: 20050194897Abstract: There is provided a polymer electroluminescent device, which comprises a transparent substrate, an anode, a polymer emitting layer, a polymer insulating nanolayer and a cathode. The polymer insulating nanolayer having the dielectric constant (?) of less than 3.0 is located between the cathode and the polymer emitting layer. According to the present invention, it is possible to obtain the polymer electroluminescent device showing more improved luminance efficiency.Type: ApplicationFiled: December 29, 2004Publication date: September 8, 2005Inventors: Young Chul Kim, Jai Kyeong Kim, Jae-Woong Yu, O Ok Park, Jong Hyeok Park
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Publication number: 20040217696Abstract: A polymeric electroluminescent device suppresses photo-oxidation and enhances luminous stability and efficiency by using a nanocomposite of a luminescent polymer and metal nanoparticles as its emitting layer.Type: ApplicationFiled: October 31, 2003Publication date: November 4, 2004Inventors: Young Chul Kim, Jai Kyeong Kim, Jae-Woong Yu, O Ok Park, Jong Hyeok Park, Yong Taik Lim
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Publication number: 20040033388Abstract: Organic white-light-emitting blend materials were prepared by light-doping method and electroluminescent devices fabricated using the same, including a transparent substance, translucent electrode, white-light-emitting layer and metal electrode in order, can efficiently control Forster energy transfer in organic light-emitting materials by performing light doping, thus to fabricate a white electroluminescent device using the blend materials which can emit white-light with high efficiency. The white-light-emitting blend materials can be obtained by the light-doping method, in which the energy transfer occurs only between a host which is a donor and each dopant which is an acceptor, while the energy transfers between dopants are efficiently blocked.Type: ApplicationFiled: August 5, 2003Publication date: February 19, 2004Applicant: Korea Institute of Science and TechnologyInventors: Young-Chul Kim, Hyun-Nam Cho, Tae-Woo Lee, O-Ok Park, Jai-Kyeong Kim, Jae-Woong Yu
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Patent number: 6344286Abstract: A diacetylene-based polymer of the following formula (I): wherein, Ar represents a light emitting group. The present invention also provides an electroluminescence device having a structure of anode/luminescent layer/cathode added with a transfer layer and/or a reflection layer, if necessary, in which the luminescent layer is made of the diacetylene-based polymer containing the light emitting group. The polymer of the present invention can be easily blended with a variety of macromolecules for general use.Type: GrantFiled: August 19, 1999Date of Patent: February 5, 2002Assignees: Hanwha Chemical Corporation, Korea Institute of Science and TechnologyInventors: Chung Yup Kim, Hyun Nam Cho, Dong Young Kim, Young Chul Kim, Jae-Min Hong, Jai Kyeong Kim, Jae-Woong Yu