Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.

Abstract: Disclosed herein are compounds of Formula (I), or pharmaceutically acceptable salts thereof, that are inhibitors of Polo Like Kinase 4 (PLK4). Also disclosed herein are pharmaceutical compositions comprising the compounds of Formula (I), or pharmaceutically acceptable salts thereof, and one or more pharmaceutically acceptable excipients. Further disclosed herein are methods of treating cancer in a subject in need thereof, comprising administering to the subject an amount of a compound of Formula (I), or a pharmaceutically acceptable salt thereof.

Abstract: The present invention relates to a method of roll-to-roll manufacturing of a 3D-patterned microstructure. Further, the present invention relates to a 3D-patterned microstructure obtained by the method. In addition, the present invention relates to a use of a 3D-patterned microstructure manufactured according to the method. Furthermore, the present invention relates to an apparatus for manufacturing a 3D-patterned microstructure, the apparatus being configured to carry out the method.

Abstract: A capacitive sensor system configured to measure capacitance, including a sample volume, a sample capacitive sensor configured to measure the capacitance of the sample volume without physical contact between the sample capacitive sensor and the sample volume, a control capacitive sensor, a differential sensing subsystem configured to measure a control sensor volume using the control capacitive sensor, and electrical circuitry connected to both the control capacitive sensor and the sample capacitive sensor.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive an indication of an antenna port mapping from a network entity. The antenna port mapping may be between a tracking reference signal and a corresponding reference signal, the antenna port mapping indicating a mapping of a tracking reference signal port to a plurality of reference signal antenna ports associated with the corresponding reference signal. The UE may receive a tracking reference signal via the tracking reference signal port based on the antenna port mapping. The UE may perform a channel measurement procedure using the tracking reference signal based on the mapping.

Abstract: Methods, systems, and devices for wireless communications are described. In some wireless communications systems, a user equipment (UE) and a network entity may utilize multi-port mobility reference signals to assist with spatial based mobility procedures. The UE may receive a reference signal that is associated with multiple antenna ports. The UE may measure a multi-dimensional channel response based on the reference signal. The multi-dimensional channel response may be associated with measured channel metrics corresponding to the multiple antenna ports. The UE may transmit a report that includes a channel measurement vector based on the multi-dimensional channel response. The channel measurement vector may indicate multiple measured channel metrics for one or more dimensions of the multi-dimensional channel response. The network entity may transmit a message that indicates one or more metrics associated with mobility management for the UE based on the report that indicates the channel measurement vector.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: A reshift unit within a computer system is configured to store repair information associated with random-access memory (RAM) modules that reside in different power regions. When one or more RAM modules in a given power region need to be repaired, the reshift unit identifies a portion of the repair information that is relevant to those RAM modules. The reshift unit then transmits that portion to the RAM modules, thereby repairing those RAM modules. Accordingly, RAM modules in a given power region can be repaired independently of RAM modules in other power regions. Advantageously, RAM modules can be repaired between cold boots without implementing the slow repair procedure performed by the fuse block during cold boot.

Abstract: A front end client-server application configured to synchronize requirements between a requirements repository and a testing repository. The front end client-server application validates a requirement, processes at least one filter associated with the requirement, determines a requirement type of the requirement, and processes the requirement. In addition, the method comprises updating a testing application in accordance with the processed requirement. In addition, it can be determined whether a plurality of requirements received by the front end client-server application that need to be synchronized contain traceability relationships. If so, the front end client-server application replicates the traceability relationship between the requirements to be synchronized and any relevant, existing requirements at the testing repository. Furthermore, the front end client-server application allows a user to customize the requirements synchronization process.

Abstract: A ceramic-copper foil bonding method includes wet-oxidizing a copper foil such that a surface of the copper foil is oxidized to a copper oxide layer, contacting the copper oxide layer with a surface of a ceramic substrate, and bonding the copper oxide layer of the copper foil to the surface of the ceramic substrate by heat treatment. Preferably, a protective layer is provided on an opposite surface of the copper foil so that the opposite surface is not oxidized during wet-oxidizing the copper foil.

Abstract: A color filter for a liquid crystal display comprising a pair of substrates each having a transparent electrode formed thereon is provided. The color filter comprising coloring materials and resins provided on at least one of the substrates, further comprises at least one dye selected from among acid red 52, acid red 486 and rhodamine 6 GCT.