Patents by Inventor Jae Yee

Jae Yee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220403698
    Abstract: A slim double-skin structure according to one aspect of the present invention may comprise: a window frame, an outer window sash frame provided on an outdoor side and coupled to the window frame, an outer glass provided on the outer window sash frame, an inner window sash frame provided on an indoor side and coupled to the window frame, an inner glass provided on the inner window sash frame, an awning film provided in a hollow layer formed between the outer glass and the inner glass to serve as a shading, and a case-type glass fixing frame which is provided in the outer window sash frame so as to be located in the hollow layer and fixes the outer glass to the outer window sash frame concurrently with building-in and guiding the awning film.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 22, 2022
    Inventors: Keon Ho LEE, Jurng Jae YEE, Seong Hoon KEE, Dong Keon KIM
  • Publication number: 20140061908
    Abstract: A plastic ball grid array package having a reinforcement resin that may address the problem of delamination and cracks in a boundary region between a sealing resin and a substrate. The reinforcement resin is formed at an outer region of a sealing resin and has a height that is lower than that of the sealing resin. The reinforcement resin may be formed of the same material used to form the sealing resin and has a structure completely covering a first surface of the substrate. Accordingly, cracks and delamination defects of the semiconductor package may be reduced by absorbing stress that occurs by physical impact in a boundary region between the substrate and the sealing resin.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 6, 2014
    Applicant: SIGNETICS KOREA CO., LTD
    Inventors: Hyo Jae YEE, Chang Young LEE, Myun Soo KIM
  • Publication number: 20080036055
    Abstract: A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. A semiconductor package fabricated using the lead frame and a fabrication method for the semiconductor package are also disclosed.
    Type: Application
    Filed: March 1, 2006
    Publication date: February 14, 2008
    Inventors: Jae Yee, Young Chung, Jae Lee, Terry Davis, Chung Han, Jae Ku, Jae Kwak, Sang Ryu
  • Publication number: 20050062148
    Abstract: A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 24, 2005
    Inventors: Seong Seo, Young Chung, Jong Paek, Jae Ku, Jae Yee
  • Patent number: 5893733
    Abstract: An electrostatic-discharge (ESD) protecting circuit of a semiconductor device prevents damage from an ESD applied to an internal circuit through an input or output pad. The thickness of respective gate insulating layers of respective active devices of the electrostatic-discharge protecting circuit and internal circuit, which are formed within a given radius in the range of about 350 .mu.m to about 1000 .mu.m from the electrostatic-discharge protecting circuit, is thicker than the thickness of gate insulating layers of active devices formed outside the radius.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: April 13, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Hyeok Jae Yee
  • Patent number: 5818087
    Abstract: An electrostatic-discharge (ESD) protecting circuit of a semiconductor device prevents damage from an ESD applied to an internal circuit through an input or output pad. The thickness of respective gate insulating layers of respective active devices of the electrostatic-discharge protecting circuit and internal circuit, which are formed within a given radius in the range of about 350.mu.m to about 1000.mu.m from the electrostatic-discharge protecting circuit, is thicker than the thickness of gate insulating layers of active devices formed outside the radius.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: October 6, 1998
    Assignee: LG Semicon, Ltd.
    Inventor: Hyeok Jae Yee