Abstract: Disclosed is a wireless power transfer pairing method and apparatus for concurrently performing a pairing procedure in a V2G WPT fine positioning procedure. The wireless power transfer pairing method comprises a step of, when an LF signal indicating that a secondary device of an electric vehicle is positioned within an alignment tolerance area on a primary device of an electric vehicle power supply device is detected, parking the electric vehicle, transmitting, to a supply equipment communication controller (SECC), a fine positioning request message in which a result code parameter is configured as a success, and transmitting, immediately after receiving from the SECC, a fine positioning response message in which a response code parameter is configured as OK, a pairing request message in which an identifier code parameter is configured as a pairing identification code and an EV processing parameter is configured as termination, to the SECC.

Abstract: The present invention provides an apparatus for managing atopic dermatitis based on a learning model and a method therefor.

Abstract: A liquid crystal display device includes a substrate, first through third thin-film transistors (“TFTs”) disposed on the substrate, and first and second sub-pixel electrodes disposed above the first through third TFTs. The second and third TFTs share a single output terminal as their output terminals, the first sub-pixel electrode is electrically connected to an output terminal of the first TFT, and the second sub-pixel electrode is electrically connected to the single output terminal of the second and third TFTs.

Abstract: A liquid crystal display device includes a substrate, first through third thin-film transistors (“TFTs”) disposed on the substrate, and first and second sub-pixel electrodes disposed above the first through third TFTs. The second and third TFTs share a single output terminal as their output terminals, the first sub-pixel electrode is electrically connected to an output terminal of the first TFT, and the second sub-pixel electrode is electrically connected to the single output terminal of the second and third TFTs.

Abstract: A liquid crystal display device includes a substrate, first through third thin-film transistors (“TFTs”) disposed on the substrate, and first and second sub-pixel electrodes disposed above the first through third TFTs. The second and third TFTs share a single output terminal as their output terminals, the first sub-pixel electrode is electrically connected to an output terminal of the first TFT, and the second sub-pixel electrode is electrically connected to the single output terminal of the second and third TFTs.

Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.

Abstract: A liquid crystal display includes: a substrate; a gate line disposed on the substrate; a storage voltage line disposed on the substrate and extending substantially parallel to the gate line; a data line disposed on the substrate; a reference voltage line disposed on the substrate and extending substantially parallel to the data line; first and second subpixel electrodes disposed in a pixel area; a first switching element connected to the gate line, the data line, and the first subpixel electrode; a second switching element connected to the gate line, the data line, and the second subpixel electrode; and a third switching element connected to the second subpixel electrode and the reference voltage line, wherein the storage voltage line and the reference voltage line are not connected to each other.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.

Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.

Abstract: A display apparatus includes: a first substrate including a display area and a non-display area adjacent to the display area; a second substrate facing the first substrate; a display device disposed between the first substrate and the second substrate; and a fan-out line, disposed in the non-display area, to apply a display signal to the display device. The fan-out line includes: a first conductive layer; and a second conductive layer disposed on the first conductive layer, the second conductive layer being electrically connected to the first conductive layer. A width of the first conductive layer is different from a width of the second conductive layer.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and an opposing second substrate; a first pixel electrode and a second pixel electrode disposed in a pixel area, on the first substrate, and including a plurality of branch electrodes; and a liquid crystal layer interposed between the first and second electrodes. Branches electrode of the first pixel electrode and the second pixel electrode are interlaced. The first pixel electrode has an extension disposed adjacent to the center of the pixel area, and a minimum distance between the extension and the adjacent branch electrode is different from an average minimum between the adjacent branch electrodes.

Abstract: A liquid crystal display includes a first substrate and a second substrate facing the first substrate, a gate line and a data line disposed on the first substrate, and a pixel electrode disposed on the first substrate. The pixel electrode is connected to the gate line and the data line, and includes subregions. The liquid crystal display further includes a storage electrode disposed on the first substrate overlapping the pixel electrode to form a storage capacitor, a common electrode disposed on the second substrate, and a liquid crystal layer interposed between the pixel electrode and the common electrode and including liquid crystal molecules disposed therein. The pixel electrode includes a stem defining boundaries between the subregions, and a width of the stem changes from a center portion of the pixel electrode to a peripheral portion of the pixel electrode.

Abstract: A liquid crystal display includes a first substrate, a second substrate, a liquid crystal layer between the substrates and including liquid crystal molecules, a first pixel electrode, and a second pixel electrode. The pixel electrodes each include a stem at an edge of a pixel area, and a plurality of branches extended from the stem. The branches of the pixel electrodes are alternately disposed. The liquid crystal display further includes a first region including a first interval between the branches of the first pixel electrode and adjacent branches of the second pixel electrode, and a second region including a second interval between the branches of the first pixel electrode and the adjacent branches of the second pixel electrode which is smaller than the first interval. The first region is where the stems of the first pixel electrode and the second pixel electrode are not disposed.

Abstract: A liquid crystal display includes first and second substrates facing each other, a liquid crystal layer between the substrates, first and second thin film transistors on the first substrate, and first and second pixel electrodes connected to the first and second thin film transistors, respectively, on the first substrate. A transverse center line bisects the first and second pixel electrodes into upper and lower portions. The first and second pixel electrodes include a plurality of branches which alternate. First and second regions include first and second intervals between adjacent branches of the first and second pixel electrodes, respectively, the first interval being larger then the second interval. At least one of the branches includes a first portion forming a first angle with the transverse center line, and a second portion forming a second angle with the transverse center line different from the first angle.

Abstract: A liquid crystal display includes: a substrate; a gate line disposed on the substrate; a storage voltage line disposed on the substrate and extending substantially parallel to the gate line; a data line disposed on the substrate; a reference voltage line disposed on the substrate and extending substantially parallel to the data line; first and second subpixel electrodes disposed in a pixel area; a first switching element connected to the gate line, the data line, and the first subpixel electrode; a second switching element connected to the gate line, the data line, and the second subpixel electrode; and a third switching element connected to the second subpixel electrode and the reference voltage line, wherein the storage voltage line and the reference voltage line are not connected to each other.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and an opposing second substrate; a first pixel electrode and a second pixel electrode disposed in a pixel area, on the first substrate, and including a plurality of branch electrodes; and a liquid crystal layer interposed between the first and second electrodes. Branches electrode of the first pixel electrode and the second pixel electrode are interlaced. The first pixel electrode has an extension disposed adjacent to the center of the pixel area, and a minimum distance between the extension and the adjacent branch electrode is different from an average minimum between the adjacent branch electrodes.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate and an opposing second substrate; a first pixel electrode and a second pixel electrode disposed in a pixel area, on the first substrate, and including a plurality of branch electrodes; and a liquid crystal layer interposed between the first and second electrodes. Branches electrode of the first pixel electrode and the second pixel electrode are interlaced. The first pixel electrode has an extension disposed adjacent to the center of the pixel area, and a minimum distance between the extension and the adjacent branch electrode is different from an average minimum between the adjacent branch electrodes.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.