Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

Abstract: The present disclosure relates to a time-division multiplexing (TDM)-based multi-channel electrocardiogram measurement apparatus and method, which remove the influence of power line interference in a way to implement multiple channels by using a TDM method, remove an electrode DC offset (EDO) through a pre-charged capacitor, and periodically take a current out or supply a current. The TDM-based multi-channel electrocardiogram measurement apparatus and method robust against power line interference according to the present disclosure have advantages in that it can measure electrocardiogram by using multiple channels with low power and high integration based on TDM, can perform contactless measurement because an EDO is efficiently eliminated and high impedance is satisfied, and has a characteristic robust against power line interference.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: The present disclosure provides a cryptographic processor device capable of performing the post-quantum cryptographic encryption with in a high speed with low power, allowing a change of encryption parameters, and handling various cryptographic protocols. The cryptographic processor device executing polynomial vector operations required for a post-quantum cryptography includes: a polynomial memory bank configured to store a plurality of polynomial vectors; and an arithmetic and logic operator configured to perform operation on the polynomial vectors.

Abstract: An exemplary embodiment of the present disclosure provides a physically unclonable function (PUF) cell capable of exhibiting a stable performance and showing an excellent repeatability while being less affected by environmental factors such as a noise, temperature, and bias voltage. The PUF cell generates an output value by combining a scheme of amplifying a threshold voltage difference and a scheme of amplifying an oscillation frequency difference. In an oscillator that generates oscillation signals of different frequencies, the frequency difference of the oscillation signals is amplified by alternately supplying bias voltages of different magnitudes generated by utilizing the threshold voltage difference to a plurality of stages in the oscillator.

Abstract: The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.

Abstract: A neuromorphic system includes a first neuromorphic layer configured to perform a forward operation with an input signal and a first weight, a first operation circuit configured to perform a first operation on a result of the forward operation of the first neuromorphic layer, a second neuromorphic layer configured to perform a forward operation with an output signal of the first operation circuit and a second weight, a second operation circuit configured to perform a second operation on a result of the forward operation of the second neuromorphic layer, a first weight adjustment amount calculation circuit configured to calculate a first weight adjustment amount, and a second weight adjustment amount calculation circuit configured to calculate a second weight adjustment amount.

Abstract: The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.

Abstract: An electronic circuit includes first to third transistors. The first transistor has a first channel width and a first channel length and generates a first potential difference by passing an operating current based on a first operating voltage. The second transistor has a second channel width and a second channel length and generates a second potential difference based on the operating current. The third transistor generates a third potential difference based on a second operating voltage and the operating current. A sum of a level of the first operating voltage and a level of the first potential difference corresponds to a sum of a level of the second operating voltage, a level of the second potential difference, and a level of the third potential difference. The first channel width is greater than the second channel width, or the first channel length is longer than the second channel length.

Abstract: Disclosed are a method and an apparatus for detecting spike event or transmitting spike event information generated in a neuromorphic chip. The apparatus for detecting spike event generated in a neuromorphic chip may detect spike event information for a plurality of neurons included in the neuromorphic chip based on a neuron group.

Abstract: An electronic circuit includes first to third transistors. The first transistor has a first channel width and a first channel length and generates a first potential difference by passing an operating current based on a first operating voltage. The second transistor has a second channel width and a second channel length and generates a second potential difference based on the operating current. The third transistor generates a third potential difference based on a second operating voltage and the operating current. A sum of a level of the first operating voltage and a level of the first potential difference corresponds to a sum of a level of the second operating voltage, a level of the second potential difference, and a level of the third potential difference. The first channel width is greater than the second channel width, or the first channel length is longer than the second channel length.

Abstract: The present invention relates to a smart remotely controlled contact lens for diagnosing and treating diseases by using a micro-LED. The present invention can diagnose and treat diseases by using a micro-LED or -OLED disposed in a contact lens. Further, the present invention can treat various diseases by using signals according to light wavelengths detected through a photodetector to control drug release from a drug delivery system in the contact lens. The drug delivery system that is a small-sized ocular insert can be electrically controlled. Accordingly, drug can be released from the drug delivery system at a desired time, and thus the drug delivery system can be applied to treatment of various diseases. Further, the photodetector can detect the therapeutic effect in real time through light reflected from a treated target cell, and thus the disease progression in a patient can be easily and quickly checked.

Abstract: The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system. The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range. Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.

Abstract: A neuromorphic system includes a first neuromorphic layer configured to perform a forward operation with an input signal and a first weight, a first operation circuit configured to perform a first operation on a result of the forward operation of the first neuromorphic layer, a second neuromorphic layer configured to perform a forward operation with an output signal of the first operation circuit and a second weight, a second operation circuit configured to perform a second operation on a result of the forward operation of the second neuromorphic layer, a first weight adjustment amount calculation circuit configured to calculate a first weight adjustment amount, and a second weight adjustment amount calculation circuit configured to calculate a second weight adjustment amount.

Abstract: The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Abstract: Disclosed are a method and an apparatus for detecting spike event or transmitting spike event information generated in a neuromorphic chip. The apparatus for detecting spike event generated in a neuromorphic chip may detect spike event information for a plurality of neurons included in the neuromorphic chip based on a neuron group.

Abstract: Disclosed are a method and an apparatus for detecting spike event or transmitting spike event information generated in a neuromorphic chip. The apparatus for detecting spike event generated in a neuromorphic chip may detect spike event information for a plurality of neurons included in the neuromorphic chip based on a neuron group.

Abstract: The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system. The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range. Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.

Abstract: The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less insensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Abstract: Provided is a technology for reducing hardware cost and enabling on-chip learning in a neuromorphic system. A synapse array includes a plurality of synapse circuits, and at least one of the plurality of synapse circuits includes at least bias transistor and a switch connected in series. Synapse circuits in the same row and column direction of the synapse array are connected to each other through a shared membrane line, and a charge amount proportional to a multiplication accumulation operation required for a forward or backward operation is supplied through the membrane line and is converted into a final digital value for output through an analog to digital converter. A virtual look-up table performs in advance a calculation required for a synapse weight update for learning of at least one column of the synapse array and is updated, so that the amount of a calculation required for entire learning is reduced.