Abstract: Disclosed herein is an apparatus and method for detecting an emotional change through facial expression analysis. The apparatus for detecting an emotional change through facial expression analysis includes a memory having at least one program recorded thereon, and a processor configured to execute the program, wherein the program includes a camera image acquisition unit configured to acquire a moving image including at least one person, a preprocessing unit configured to extract a face image of a user from the moving image and preprocess the extracted face image, a facial expression analysis unit configured to extract a facial expression vector from the face image of the user and cumulatively store the facial expression vector, and an emotional change analysis unit configured to detect a temporal location of a sudden emotional change by analyzing an emotion signal extracted based on cumulatively stored facial expression vector values.

Abstract: An image processing device including: a gain value manager for generating white gain values corresponding to a plurality of positions, based on a sensing result of a predetermined white image; a target pixel manager for detecting saturated pixels, based on pixel values received from an external device, and determining target pixels as saturated white pixels of which each have a pixel value that indicates that the saturated white pixel is saturated, based on peripheral pixels of the saturated white pixels among the detected saturated pixels; and a target pixel corrector for changing pixel values of the target pixels, based on the white gain values and pixel values of the peripheral pixels.

Abstract: A monoclonal antibody or an antigen-binding fragment thereof according to an embodiment of the present invention can bind to lymphocyte-activation gene 3 (LAG-3) including a heavy chain variable region and a light chain variable region and inhibit the activity thereof. Thus it is expected to be useful for the development of immunotherapeutic agents for various disorders that are associated with LAG-3.

Abstract: Provided herein may be an image sensing device and a method of operating the same. The image sensing device may include an image sensor configured to acquire an image including a plurality of pixel values, a memory configured to store reference gain values of each of a plurality of block areas included in the image, and an image processor configured to calculate gain values included in each of the plurality of block areas using the reference gain values and to output a correction image in which the reference gain values and the gain values are applied to the plurality of pixel values, wherein the block areas include a first block area and a second block area having a shorter distance from a center of the image than the first block area and having a size greater than that of the first block area.

Abstract: Provided herein may be an image sensing device and a method of operating the same. An image sensing device may include an image sensor obtaining an image using a plurality of pixels, and an image processor configured to use pixel values included in a region of interest included in the image to generate a gain table including gain table values corresponding to a first resolution, convert the gain table into a target table including target table values corresponding to a second resolution which is lower than the first resolution, and cancel noise included in the image based on the target table.

Abstract: Provided herein may be an image sensing device and a method of operating the same. The image sensing device may include an image sensor configured to acquire an image including a plurality of pixel values, a memory configured to store reference gain values of each of a plurality of block areas included in the image, and an image processor configured to calculate gain values included in each of the plurality of block areas using the reference gain values and to output a correction image in which the reference gain values and the gain values are applied to the plurality of pixel values, wherein the block areas include a first block area and a second block area having a shorter distance from a center of the image than the first block area and having a size greater than that of the first block area.

Abstract: A grid gain calculation circuit includes a region setting component suitable for setting a grid region corresponding to a pixel array; a virtual grid point setting component suitable for setting virtual grid points with respect to outer grid points located on a border of a grid region and with respect to an inner grid point located in an inner area of the grid region close to the outer grid points; and a gain calculation component suitable for calculating a gain of the outer grid points based on a gain of the inner grid point and a gain of the virtual grid points.

Abstract: A grid gain calculation circuit includes a region setting component suitable for setting a grid region corresponding to a pixel array; a virtual grid point setting component suitable for setting virtual grid points with respect to outer grid points located on a border of a grid region and with respect to an inner grid point located in an inner area of the grid region close to the outer grid points; and a gain calculation component suitable for calculating a gain of the outer grid points based on a gain of the inner grid point and a gain of the virtual grid points.

Abstract: A method for processing an image signal, an image signal processor, and an image sensor chip are disclosed. A method for processing an image signal includes generating Bayer order status information indicating whether a Bayer order of a Bayer pattern image has been changed, based on translation information of gyro information, performing translation correction about the Bayer pattern image using the translation information, and performing interpolation about the Bayer pattern image in which the translation correction has been performed, based on the Bayer order status information.

Abstract: A method for processing an image signal, an image signal processor, and an image sensor chip are disclosed. A method for processing an image signal includes generating Bayer order status information indicating whether a Bayer order of a Bayer pattern image has been changed, based on translation information of gyro information, performing translation correction about the Bayer pattern image using the translation information, and performing interpolation about the Bayer pattern image in which the translation correction has been performed, based on the Bayer order status information.

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract: Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same.

Abstract: A semiconductor device includes a substrate having a trench, a sidewall liner that covers inner walls of the trench, a doped oxide film liner on the sidewall liner in the trench, and a gap-fill insulating film that buries the trench on the doped oxide film liner. In order to form the doped oxide film liner, an oxide film liner is doped with a dopant under a plasma atmosphere. Related methods are also disclosed.

Abstract: The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract: Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drain regions and the channel region and, particularly, between deep source/drain regions and the halo regions. Buried isolation regions between the deep source/drain regions and the channel region minimize drain induced barrier lowering (DIBL) as well as punch through. Additionally, because the deep source/drain regions and halo regions are separated by the buried isolation regions, side-wall junction capacitance and junction leakage are also minimized.

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

Abstract: There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.

Abstract: An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask layer and on the sidewall of the trench. A trench liner layer is formed on the oxide layer. An insulating filler layer is formed in the trench in the semiconductor substrate, on which the trench liner layer is formed, so as to fill the trench. The insulating mask layer is removed. According to the isolation method for a semiconductor device, it is possible to reduce dents from occurring along the edge of the trench, reduce a bird's beak type oxide layer from occurring at an interface between the insulating mask layers, decrease the leakage current, or improve the electrical characteristics, such as threshold voltage.