Abstract: A swirl chamber-type diesel engine includes a secondary combustion chamber assembly coupled to a cylinder head to define a secondary combustion chamber having, on an inner wall surface thereof, a curved swirl induction part, and a connecting passage formed at a lower end of the swirl induction part, and a piston defining a primary combustion chamber and including a trench part being in communication with the connecting passage, and clover parts formed at both sides of the trench part, in which a guide structure is provided in the connecting passage, and the guide structure divides combustion gas, discharged from the secondary combustion chamber to the primary combustion chamber, into three portions and guides the combustion gas.

Abstract: A swirl chamber-type diesel engine includes a secondary combustion chamber assembly coupled to a cylinder head to define a secondary combustion chamber having, on an inner wall surface thereof, a curved swirl induction part, and a connecting passage formed at a lower end of the swirl induction part; and a piston defining a primary combustion chamber and including a trench part being in communication with the connecting passage, and clover parts formed at both sides of the trench part, in which a bottom surface of the clover part has a stereoscopic structure in which a height of a bottom surface in a second region, which is distant in a direction of a flow of the combustion gas at a predetermined distance from a first region into which the combustion gas is introduced from the trench part is greater than a height of a bottom surface in the first region.

Abstract: A swirl chamber-type diesel engine includes a secondary combustion chamber assembly coupled to a cylinder head to define a secondary combustion chamber having, on an inner wall surface thereof, a curved swirl induction part, and a connecting passage formed at a lower end of the swirl induction part; and a piston defining a primary combustion chamber and including a trench part being in communication with the connecting passage, and clover parts formed at both sides of the trench part, in which a bottom surface of the clover part has a stereoscopic structure in which a height of a bottom surface in a second region, which is distant in a direction of a flow of the combustion gas at a predetermined distance from a first region into which the combustion gas is introduced from the trench part is greater than a height of a bottom surface in the first region.

Abstract: A swirl chamber-type diesel engine includes a secondary combustion chamber assembly coupled to a cylinder head to define a secondary combustion chamber having, on an inner wall surface thereof, a curved swirl induction part, and a connecting passage formed at a lower end of the swirl induction part, and a piston defining a primary combustion chamber and including a trench part being in communication with the connecting passage, and clover parts formed at both sides of the trench part, in which a guide structure is provided in the connecting passage, and the guide structure divides combustion gas, discharged from the secondary combustion chamber to the primary combustion chamber, into three portions and guides the combustion gas.

Abstract: A method of fabricating an array substrate including forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by irradiating X-rays or UV rays to the oxide semiconductor layer exposed outside the gate electrode; forming an inter insulating layer on the gate electrode and having first contact holes that expose the source and drain areas; and forming source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first contact holes, respectively.

Abstract: A method of fabricating an array substrate including forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by irradiating X-rays or UV rays to the oxide semiconductor layer exposed outside the gate electrode; forming an inter insulating layer on the gate electrode and having first contact holes that expose the source and drain areas; and forming source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first contact holes, respectively.

Abstract: A method of fabrication an array substrate which includes foaming an oxide semiconductor layer on a substrate; forming a gate insulating layer corresponding to a central portion of the oxide semiconductor layer; forming a first reactive metallic pattern and second reactive metallic patterns on the gate insulating layer and portions of the oxide semiconductor layer exposed outside the gate insulating layer, respectively; forming a gate electrode on the first reactive metallic pattern; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing heat treatment such that materials of the second reactive metallic patterns are diffused into the oxide semiconductor layer contacting the second reactive metallic patterns; forming an inter insulating layer on the gate electrode and having first contact holes that expose the second reactive metallic patterns; and forming source and drain electrodes on the inter insulating layer and contacting the second reactive metallic pa

Abstract: A method of fabrication an array substrate which includes foaming an oxide semiconductor layer on a substrate; forming a gate insulating layer corresponding to a central portion of the oxide semiconductor layer; forming a first reactive metallic pattern and second reactive metallic patterns on the gate insulating layer and portions of the oxide semiconductor layer exposed outside the gate insulating layer, respectively; forming a gate electrode on the first reactive metallic pattern; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing heat treatment such that materials of the second reactive metallic patterns are diffused into the oxide semiconductor layer contacting the second reactive metallic patterns; forming an inter insulating layer on the gate electrode and having first contact holes that expose the second reactive metallic patterns; and forming source and drain electrodes on the inter insulating layer and contacting the second reactive metallic pa

Abstract: A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.

Abstract: A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.

Abstract: A plasma etching method is performed by plasma etching an SiN layer through a mask layer to form a first wiring portion and a second wiring portion, the first and the second wiring portions having different wiring densities in the etched SiN layer, the mask having two pattern portions respectively corresponding to the first and the second wiring portions. In the plasma etching step, by using an etching gas including fluorocarbon and C2H2F4, the line width variation between the first and the second wiring portions is restrained.

Abstract: A plasma etching method is performed by plasma etching an SiN layer through a mask layer to form a first wiring portion and a second wiring portion, the first and the second wiring portions having different wiring densities in the etched SiN layer, the mask having two pattern portions respectively corresponding to the first and the second wiring portions. In the plasma etching step, by using an etching gas including fluorocarbon and C2H2F4, the line width variation between the first and the second wiring portions is restrained.

Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.