Abstract: The present disclosure relates to a pulley-integrated cable actuator and an operation method thereof, more particularly to an actuator for operating cables. The pulley-integrated cable actuator includes: a base motor; a sun gear shaft of which the lower end portion is coupled to the center of the base motor, rotating by the motor rotation, and provided with a sun gear; a planet gear set consisting of multiple planet gears that mesh with the sun gear; and a ring gear-integrated pulley where a ring gear is formed on the inner side, meshing with the planet gear, and a pulley for winding a cable is formed on the outer side. The sun gear meshes with the inner space of the planet gear set. The ring gear is integrated with the pulley. The planet gear set is placed inside the pulley, minimizing the volume.

Abstract: A battery control apparatus includes a memory for storing a criterion voltage for a battery; a measuring unit for measuring a voltage of the battery during a charging or discharging process of the battery; and a processor for comparing the measured voltage and the criterion voltage during the charging or discharging process of the battery and changing a charging C-rate or a discharging C-rate for the battery when the measured voltage corresponds to the criterion voltage.

Abstract: A holographic optical element and a method for producing the same are disclosed herein. In some embodiments, a method includes illuminating a first surface of a photopolymer resin layer, where the photopolymer resin layer comprises a photopolymer resin, illuminating a second surface of the photopolymer resin layer through a retardation layer disposed in the second surface, wherein the second surface is opposite the first surface, and recording an interference pattern in the photopolymer resin layer, wherein the interference pattern is created by interference between the first parallel laser beam and the second parallel laser beam. The holographic optical element is produced using a retardation layer to prevent an unwanted interference pattern from being formed in the process of recording an interference pattern in a photopolymer resin layer.

Abstract: A positive electrode active material and a method of making the same are disclosed herein. In some embodiments, a method includes mixing transition metal raw powders including a nickel raw powder to prepare a first mixture, where the first mixture has a molar ratio of lithium to total transition metals of 0.95 to 1.02, and where a molar ratio of nickel to total transition metals is 80 mol % or more, sintering the first mixture in an oxygen-containing atmosphere, and cooling the sintered first mixture to obtain a first sintered product, mixing the first sintered product with a second lithium raw material to prepare a second mixture, where the second mixture has molar ratio of lithium to total transition metals of 1.00 to 1.09, and sintering the second mixture in the oxygen-containing atmosphere to prepare a lithium composite transition metal oxide in the form of a single particle.

Abstract: A positive electrode active material and a method for manufacturing the same are disclosed herein. In some embodiments, a method includes mixing and grinding raw material particles to obtain ground product particles, where the raw material particles are source materials for a lithium composite transition metal oxide, sintering the ground product particles to synthesize the lithium composite transition metal oxide, and disaggregating and classifying the synthesized lithium composite transition metal oxide to obtain a positive electrode active material powder, wherein the mixing and grinding the raw materials includes placing the raw materials and beads in a chamber of a grinding device, where the grinding device includes a rotatable rotor in the chamber, and performing a dry process of mixing and grinding the raw material particles in the chamber by rotating the rotor to give kinetic energy to the beads, causing collisions between the beads and the raw material particles.

Abstract: A device and method for data rate selection in data transmission is provided, having a first register for storing an N bit data upon clocking by a first clock; a second at least one register for storing the N bit data upon clocking by a second clock, the second clock having a clock rate of two times the clock rate of the first clock; a circuit for receiving the N bit data output from the first register and outputting a first half of the N bit data during a first phase of the first clock and outputting a second half of the N bit data during a second phase of the first clock; and a multiplexer for receiving as first inputs the output of the circuit and second inputs the output of the second at least one register, wherein the multiplexer outputs the first inputs as a lower speed data and outputs the second inputs as a higher speed data based on a rate select signal.

Abstract: A device and method for data rate selection in data transmission is provided, having a first register for storing an N bit data upon clocking by a first clock; a second at least one register for storing the N bit data upon clocking by a second clock, the second clock having a clock rate of two times the clock rate of the first clock; a circuit for receiving the N bit data output from the first register and outputting a first half of the N bit data during a first phase of the first clock and outputting a second half of the N bit data during a second phase of the first clock; and a multiplexer for receiving as first inputs the output of the circuit and second inputs the output of the second at least one register, wherein the multiplexer outputs the first inputs as a lower speed data and outputs the second inputs as a higher speed data based on a rate select signal.

Abstract: A circuit for serializing parallel data of n bits, comprising a first register for storing m bits of the parallel data, M being less than N, the first register being clocked by a first clock, at least one second register other than the first register for storing at least N-M bits of the parallel data, the at least one second register being clocked by at least one second clock which is different in phase from the first clock, at least one third register for storing at least the nth and (n−1)th bits of parallel data output from the at least one second register, the third register being clocked by at least one third clock which is different in phase from the first and the second clocks, and logic gates for receiving as inputs the n bits of parallel data output from the first register and output from one or both of the at least one second register and the third register to form N serial data.