Patents by Inventor Jae Yung Jun

Jae Yung Jun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11354241
    Abstract: A memory system may include a cache memory, a nonvolatile memory, a write back wait queue, and a controller. To evict an eviction cache entry including a target transaction ID from the memory cache to the nonvolatile memory, the controller performs write back operations on cache entries respectively corresponding to waiting entries at a head of the write back wait queue until a waiting entry including the target transaction ID arrives at the head of the write back wait queue, and then performs a write back operation on the eviction cache entry.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Yung Jun, Dong Kyun Kim, Su Chang Kim, Yun Keuk Kim
  • Publication number: 20210311872
    Abstract: A memory system may include a cache memory, a nonvolatile memory, a write back wait queue, and a controller. To evict an eviction cache entry including a target transaction ID from the memory cache to the nonvolatile memory, the controller performs write back operations on cache entries respectively corresponding to waiting entries at a head of the write back wait queue until a waiting entry including the target transaction ID arrives at the head of the write back wait queue, and then performs a write back operation on the eviction cache entry.
    Type: Application
    Filed: August 27, 2020
    Publication date: October 7, 2021
    Inventors: Jae Yung JUN, Dong Kyun KIM, Su Chang KIM, Yun Keuk KIM
  • Patent number: 10776227
    Abstract: Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 15, 2020
    Assignee: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi
  • Patent number: 10372563
    Abstract: Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Young Sun Han
  • Patent number: 10325672
    Abstract: Disclosed are a memory apparatus having a plurality of information storage tables managed by separate virtual regions and a control method thereof. That is, a fault repair is applied in a memory system having a plurality of information storage tables managed by a separate virtual region, so that the entire information storage space is uniformly used for every region to improve a performance of the entire system and maximize efficiency of the information storage space by utilizing the information storage space.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 18, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi, Young Sun Han
  • Patent number: 10176060
    Abstract: Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: January 8, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi
  • Publication number: 20180217774
    Abstract: Disclosed are a virtual memory management apparatus for avoiding error cells in a main memory and a method thereof. That is, according to the present invention, it is possible to prevent a data loss or malfunction from occurring by allocating and releasing a stack frame in a way a block including the error cells to be located between the stack frames in case of a stack region, processing the block including the error cells to be in an allocated state in a heap region memory management data structure in case of a heap region, allocating the pages including error cells to programs not used frequently via profile in case of code memory, and allocating physical memory page including the error cells to unused space of last page in case of file-mapped memory.
    Type: Application
    Filed: April 7, 2017
    Publication date: August 2, 2018
    Applicant: Korea University Research and Business Foundation
    Inventors: Seon Wook KIM, Yoonah PAIK, Jae Yung JUN
  • Publication number: 20180047459
    Abstract: Disclosed are a memory apparatus having a plurality of information storage tables managed by separate virtual regions and a control method thereof. That is, a fault repair is applied in a memory system having a plurality of information storage tables managed by a separate virtual region, so that the entire information storage space is uniformly used for every region to improve a performance of the entire system and maximize efficiency of the information storage space by utilizing the information storage space.
    Type: Application
    Filed: April 13, 2017
    Publication date: February 15, 2018
    Applicant: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi, Young Sun Han
  • Publication number: 20180011770
    Abstract: Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 11, 2018
    Applicant: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi
  • Publication number: 20170371753
    Abstract: Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.
    Type: Application
    Filed: January 30, 2017
    Publication date: December 28, 2017
    Applicant: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi
  • Publication number: 20170364420
    Abstract: Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.
    Type: Application
    Filed: January 30, 2017
    Publication date: December 21, 2017
    Applicant: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Young Sun Han