Abstract: A deepfake detection device may include a data input unit that receives an input image including a low-quality deepfake video, a branch-based super-resolution training unit that enhances the resolution of the input image through unsupervised super-resolution training and generates a plurality of super-resolution images having different sizes, and a multi-scale training unit that performs multi-scale training, without resolution conversion, on the plurality of super-resolution images having different sizes, respectively. The multi-scale training unit may synthesize multi-scale training results for the plurality of super-resolution images having different sizes, respectively, and determine whether the input image is a deepfake based on the multi-scale training results.

Abstract: The present disclosure relates to a tuner capable of receiving a television broadcasting signal of a wide band having an operating frequency bandwidth of 48 MHz˜1 GHz, wherein the tuner filters a radio frequency (RF) signal outputted from the low noise amplifier using a tunable filter. The tunable filter includes according to an embodiment an inductor and a variable capacitor as passive elements to reject harmonics. The tuner includes a mixer which mixes an output signal of the tunable filter with a local oscillator signal and converts the mixed signal to an In-phase and Quadrature IF signal, where the converted IF signal of I channel and Q channel is processed through an IF signal processor and is converted to an appropriate signal by a demodulator.

Abstract: The present disclosure relates to a tuner capable of receiving a television broadcasting signal of a wide band having an operating frequency bandwidth of 48 MHz˜1 GHz, wherein the tuner filters a radio frequency (RF) signal outputted from the low noise amplifier using a tunable filter. The tunable filter includes according to an embodiment an inductor and a variable capacitor as passive elements to reject harmonics. The tuner includes a mixer which mixes an output signal of the tunable filter with a local oscillator signal and converts the mixed signal to an In-phase and Quadrature IF signal, where the converted IF signal of I channel and Q channel is processed through an IF signal processor and is converted to an appropriate signal by a demodulator.

Abstract: A serializer-deserializer circuit having increased margins for setup and hold time is provided. The serializer-deserializer circuit comprises a data skew control circuit, a latch circuit, a serial converter circuit, and a phase locked loop (PLL). The data skew control circuit receives a first clock signal and a data signal, delays the data signal, and outputs a delayed data signal in response to a reference clock signal. The latch circuit latches and outputs the delayed data signal in response to the reference clock signal. The serial converter circuit receives and serializes an output signal of the latch circuit in response to the reference clock signal to output serial data. The PLL generates the reference clock signal in response to an external reference clock signal.

Abstract: A serializer-deserializer circuit having increased margins for setup and hold time is provided. The serializer-deserializer circuit comprises a data skew control circuit, a latch circuit, a serial converter circuit, and a phase locked loop (PLL). The data skew control circuit receives a first clock signal and a data signal, delays the data signal, and outputs a delayed data signal in response to a reference clock signal. The latch circuit latches and outputs the delayed data signal in response to the reference clock signal. The serial converter circuit receives and serializes an output signal of the latch circuit in response to the reference clock signal to output serial data. The PLL generates the reference clock signal in response to an external reference clock signal.

Abstract: A high-voltage tolerant interface circuit includes a terminal, first and second buffers, and a voltage controller. The first buffer includes MOS transistors having electrodes connected to the terminal, and converts and transfers the voltage level of an input signal to the terminal. The second buffer includes at least one MOS transistor having an electrode connected to the terminal, and converts a voltage level of a signal from the terminal. The voltage controller is connected to the terminal, and when a supply voltage is applied to the interface circuit, the voltage controller supplies the supply voltage to gates of the MOS transistors. When the supply voltage is not applied to the interface circuit and a voltage greater than the supply voltage is input to the terminal, the voltage controller pulls down the voltage and provides it to the gates of the MOS transistors.

Abstract: Integrated circuit buffers include an inverter and a circuit that selectively powers the inverter at a first potential (e.g., VDDL−&agr;) when the output of the inverter is at a first logic level (e.g., logic 0) and at a second higher potential (e.g., VDDL) when the output of the inverter is at a second logic level (e.g., logic 1) opposite the first logic level. The integrated circuit buffer may include an inverter configured as a PMOS pull-up transistor having a gate electrode electrically coupled to an input node (IN) and a drain electrode electrically coupled to an output node (OUT), and an NMOS pull-down transistor having a gate electrode electrically coupled to the input node and a drain electrode electrically coupled to the output node. A diode and switch are also provided to perform the selective powering operation.

Abstract: An analog/digital (A/D) converting circuit is provided that stabilizes system operation, reduces power consumption in an analog circuit region and uses a selected metal-to-metal capacitor, which has a small parasitic capacitance value. The A/D converting circuit includes a first sample/hold amplifier for sampling/holding an analog input signal, a switch for selecting one of a signal outputted from the first sample/hold amplifier and a feedback signal and an A/D sub-converter for converting an analog signal outputted from the switch to a digital signal. A multiplying D/A converting block converts an output signal from the A/D sub-converter to an analog signal and amplifies a difference value obtained between the analog signal and the analog signal outputted from the switch. A second sample/hold amplifier samples/holds a signal outputted from the multiplying D/A converting block and outputs the feedback signal to the switch.