Abstract: An example of flip-flop includes a master latch and a slave latch, and the master latch may include a first circuit configured to generate, based on a data input, a first data signal complementary to the data input and a second circuit configured to generate, based on a clock input and the first data signal, a second data signal complementary to the first data signal and a clock signal complementary to the clock input, and the slave latch may be configured to receive the clock signal through a first node and to generate a data output by latching a third data signal complementary to the second data signal based on the clock input, the second data signal, and the clock signal, and the second circuit may be configured to float the first node based on the first data signal and the third data signal.

Abstract: A flip-flop includes a clock buffer that outputs, based on a clock signal, an inverted clock signal of the clock signal and a buffer clock signal obtained by delaying a phase of the clock signal, a master latch including a scan path and a data path, the data path receiving a data signal independently of the scan path, a slave latch that generates a first driving signal based on a first latch signal from the master latch and outputs an inverted output signal based on the first latch signal, the buffer clock signal, and the first driving signal, and an output driver that outputs an output signal based on the inverted output signal.

Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.

Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.