Abstract: A semiconductor memory device including a semiconductor layer including a source area, a channel area, and a drain area arranged in a first horizontal direction on a substrate, a cell capacitor extending in the first horizontal direction on the substrate and including a lower electrode layer, a capacitor dielectric film, and an upper electrode layer connected to the source area, a bit line extending in a vertical direction on the substrate and connected to the drain area, and a gate structure covering the channel area, and the gate structure including a gate dielectric film on the channel area and a gate electrode film on the gate dielectric film, wherein in the vertical direction, a first thickness of an end of the channel area facing the source area is greater than a second thickness of another end of the channel area facing the drain area may be provided.

Abstract: A semiconductor device includes a substrate, a plurality of semiconductor patterns spaced apart from each other in a first horizontal direction on the substrate, where each of the plurality of semiconductor patterns has first side surfaces opposing each other in the first horizontal direction and second side surfaces opposing each other in a second horizontal direction, the first and second horizontal directions parallel to an upper surface of the substrate, the second horizontal direction perpendicular to the first horizontal direction, source/drain regions on the second side surfaces of each of the plurality of semiconductor patterns, a plurality of gate patterns surrounding upper surfaces, lower surfaces, and the first side surfaces of each of the plurality of semiconductor patterns, a plurality of conductive line patterns connecting the plurality of gate patterns to each other, and data storage structures in parallel to the plurality of semiconductor patterns in the second horizontal direction.

Abstract: A semiconductor device includes a substrate having first and second regions, semiconductor patterns spaced apart from each other in a first horizontal direction on the first region, wherein each of the semiconductor patterns has first side surfaces opposing each other in the first horizontal direction and second side surfaces opposing each other in a second horizontal direction, the first and second horizontal directions parallel to an upper surface of the substrate, the second horizontal direction perpendicular to the first horizontal direction, gate patterns surrounding an upper surface, a lower surface, and the first side surfaces of each of the semiconductor patterns, and a landing pattern spaced apart from the semiconductor patterns in the first horizontal direction on the second region and electrically connected to the gate patterns. The landing pattern includes a semiconductor material layer and a conductive material layer covering at least one surface of the semiconductor material layer.