Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A chip on film package includes; a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: A semiconductor package includes a package substrate, a first semiconductor device arranged on the package substrate, at least one second semiconductor device on the first semiconductor device to partially cover the first semiconductor device from a top down view, a heat dissipating insulation layer coated on the first semiconductor device and the at least one second semiconductor device, a conductive heat dissipation structure arranged on the heat dissipating insulation layer on a portion of the first semiconductor device not covered by the second semiconductor device, and a molding layer on the package substrate to cover the first semiconductor device and the at least one second semiconductor device. The heat dissipating insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure formed of an electrically and thermally conductive material.

Abstract: A chip on film package includes; a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the se

Abstract: A semiconductor package includes a package substrate, a first semiconductor device arranged on the package substrate, at least one second semiconductor device on the first semiconductor device to partially cover the first semiconductor device from a top down view, a heat dissipating insulation layer coated on the first semiconductor device and the at least one second semiconductor device, a conductive heat dissipation structure arranged on the heat dissipating insulation layer on a portion of the first semiconductor device not covered by the second semiconductor device, and a molding layer on the package substrate to cover the first semiconductor device and the at least one second semiconductor device. The heat dissipating insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure formed of an electrically and thermally conductive material.

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the se

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.

Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.

Abstract: Provided is a dynamic thermal management method performed by an application processor which stores a first dynamic voltage and frequency scaling (DVFS) table and a second DVFS table, the method including comparing a surface temperature of a mobile apparatus with a critical surface temperature, controlling performance of the application processor according to the first DVFS table when the surface temperature is less than the critical surface temperature, and controlling performance of the application processor according to the second DVFS table when the surface temperature is not less than the critical surface temperature.

Abstract: A semiconductor chip and a first heat dissipation pattern are mounted on a substrate. The first heat dissipation pattern has an opening therein and exposes the semiconductor chip therethrough. A second heat dissipation pattern including a thermal interface material (TIM) is interposed between a side surface of the semiconductor chip and the first heat dissipation pattern.

Abstract: The present invention relates to an opening/shutting means for intake valves of a car includes a rocker arm shaft, a plurality of rocker arms having respectively slide holes through which the rocker arm shaft passes, one end part of the rocker arm opening/shutting the intake valves and the other end part of the rocker arm being in contact with a cam on a cam shaft, an oil chamber provided at least at one end part of the rocker arm shaft to receive oil therein through an oil inlet connected with a gallery hole of a cylinder head, and a balance spring provided in one part of the oil chamber to support the rocker arm shaft against the oil pressure, wherein the amount of intake gas is automatically controlled according to varying speeds by the lift degree of the rocker arm pivoting on the rocker arm shaft which reciprocates in the slide hole of the rocker arm according to the balance between the oil pressure and the elasticity of the balance spring, so that the fuel consumption is reduced and the optimum engine o