Abstract: A semiconductor package may comrpise a substrate, a chip structure on the substrate, a passive element structure in the substrate and including a passive element, and a stiffening structure at least partially overlapping the passive element structure. A top surface of the passive element may be below a top surface of the substrate.

Abstract: Disclosed is a semiconductor package comprising an interposer, a first semiconductor die below the interposer, and a first dummy die, a second dummy die, and a second semiconductor die over the interposer. The first semiconductor die, the second semiconductor die, the first dummy die, and the second dummy die overlap the interposer. The first semiconductor die overlaps the second semiconductor die. The second semiconductor die is between the first dummy die and the second dummy die.

Abstract: A semiconductor package includes a redistribution line structure that has a redistribution line layer. A first semiconductor chip is disposed above the redistribution line structure and includes a first region with a first thickness and a second region with a second thickness that is less than the first thickness. A sub-semiconductor package includes a second semiconductor chip and is disposed above the second region of the first semiconductor chip. A silicon through via penetrates the second region of the first semiconductor chip and electrically connects the sub-semiconductor package with the redistribution line structure. A sealant seals at least a portion of each of the first semiconductor chip and the sub-semiconductor package. The sub-semiconductor package is disposed within the second region of the first semiconductor chip.

Abstract: A stacked semiconductor package includes: a first semiconductor package that includes a first region and a second region and includes a semiconductor chip including a first element at the first region and a second element at the second region; a second semiconductor package on the first region of the first semiconductor package; and a member for heat dissipation at the second region of the first semiconductor package and overlapping at least a portion of the second element in a vertical direction perpendicular to an in-plane direction of the first semiconductor package.

Abstract: Disclosed are heat radiation devices and semiconductor apparatuses including the same. The semiconductor apparatus comprises a substrate, a plurality of semiconductor devices on the substrate and arranged in a first direction as a horizontal direction, and a heat radiation device on the plurality of semiconductor devices. The heat radiation device provides a plurality of vapor chambers. The plurality of vapor chambers are spaced apart from each other in the first direction and are not connected to each other.

Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip bumps between the first package substrate and the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a molding member which covers the plurality of second semiconductor chips, on the first semiconductor chip, and a thermoelectric cooling layer attached onto a surface of the first semiconductor chip. The thermoelectric cooling layer includes a cooling material layer extending along the surface of the first semiconductor chip, a first electrode pattern which surrounds the plurality of first chip bumps from a planar viewpoint, in the cooling material layer, and a second electrode pattern which surrounds the first electrode pattern from the planar viewpoint, in the cooling material layer.

Abstract: A semiconductor package includes a substrate, a semiconductor die on the substrate, a heat spreader covering the semiconductor die. The heat spreader includes an upper plate portion, a base portion, and a sidewall portion connecting the upper plate portion to the base portion. The upper plate portion and the sidewall portion define an underlying cavity. The base portion is disposed on the substrate, extends from an exterior side of the sidewall portion in a horizontal direction, includes a plurality of first through holes, has a bottom surface at the same level as a bottom surface of the sidewall portion, and has a height in a vertical direction from a lowermost portion to an uppermost portion thereof less than or equal to that of the sidewall portion.

Abstract: A semiconductor package includes a redistribution layer structure, a semiconductor structure on the redistribution layer structure, at least one heat dissipation structure on the semiconductor structure, where the at least one heat dissipation structure may include a first epoxy molding compound, a molding material for molding the semiconductor structure and the at least one heat dissipation structure, on the redistribution layer structure, where the molding material may include a second epoxy molding compound, where the first epoxy molding compound may have higher thermal conductivity than the second epoxy molding compound.

Abstract: A semiconductor design optimization system that includes: a data base configured to store design data, a training data preprocessing unit configured to preprocess the design data and generate training data, a data learning unit configured to generate a physical property prediction model by training using the training data, a physical property prediction unit configured to generate predicted physical property data including information associated with predicted physical property values for each region of a semiconductor device to be fabricated, wherein the physical property prediction unit is configured to input, into the physical property prediction model, input data including information associated with design drawings of the semiconductor device to be fabricated, and a layout generator configured generate a design layout optimized to distribute the predicted physical property values for each region of the semiconductor device to be fabricated by modifying the design drawings based on the predicted physical

Abstract: A semiconductor package may include a lower structure, a first semiconductor chip on the lower structure, the first semiconductor chip including a hot spot, a second semiconductor chip horizontally spaced apart from the first semiconductor chip on the lower structure, and a connection chip in the lower structure and connecting the first and second semiconductor chips to each other. The hot spot may vertically overlap the connection chip.

Abstract: A semiconductor package with improved thermal properties is provided. The semiconductor package includes a first package including a first die, an interposer on the first package and including a first area and a second area. A second package is on a top face of the interposer in the second area, and a thermal diffusion structure is on a top face of the interposer in the first area. The thermal diffusion structure is configured so that heat generated in the first die is discharged through the thermal diffusion structure.

Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A semiconductor package including a substrate and at least one semiconductor chip on the substrate may be provided. The substrate may include a body layer having a top surface and a bottom surface, a first thermal conductive plate on the top surface of the body layer, the first thermal conductive plate connected to a ground terminal of the semiconductor chip, and a thermal conductive via penetrating the body layer and being in contact with the first thermal conductive plate.

Abstract: A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

Abstract: A semiconductor package includes: a first thermal pillar disposed on a package substrate, and having an opening; a first chip stack disposed on the package substrate and in the opening of the first thermal pillar, and including a first lateral surface; a semiconductor chip disposed on the package substrate and in the opening, wherein the semiconductor chip is spaced apart from the first chip stack; and a first heat transfer film disposed between the first thermal pillar and the first lateral surface of the first chip stack.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip bumps between the first package substrate and the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a molding member which covers the plurality of second semiconductor chips, on the first semiconductor chip, and a thermoelectric cooling layer attached onto a surface of the first semiconductor chip. The thermoelectric cooling layer includes a cooling material layer extending along the surface of the first semiconductor chip, a first electrode pattern which surrounds the plurality of first chip bumps from a planar viewpoint, in the cooling material layer, and a second electrode pattern which surrounds the first electrode pattern from the planar viewpoint, in the cooling material layer.

Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.