Abstract: The present disclosure relates to a DC-DC converter, a vehicle, and a control method including the same, and more particularly, to a DC-DC converter, a vehicle, and a control method including the same capable of effectively detecting and responding to an interlock failure of a connector.

Abstract: A DC-DC converter, a vehicle including the converter, and a controlling method thereof are provided. The DC-DC converter includes a first capacitor connected to a first DC terminal, a second capacitor connected to a second DC terminal, a plurality of converting circuits each including at least an inductor and a plurality of switching elements, and connected to each other in parallel between the first capacitor and the second capacitor, and a controller configured to control an ON/OFF state of the plurality of switching elements provided of each of the converting circuits. When external power connection with respect to each of the first DC terminal and the second DC terminal is disconnected, the controller is configured to control states of the plurality of switching elements to sequentially provide a plurality of different discharge paths between opposite terminals of the second capacitor via the plurality of converting circuits.

Abstract: A vehicle is provided that includes a DC converter having a first end connected to a fuel cell, a second end connected to a high-voltage battery, and at least one switching element connected between the first end and the second end, a fuel cell control unit which controls an activation state of a running command for start of the fuel cell based on an on-off state of vehicle start, and a converter controller which controls a running state of the DC converter according to an initial start sequence, a shutdown sequence, or a restart sequence for the fuel cell based on the activation state of the running command.

Abstract: A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.

Abstract: A tile-based rendering method includes receiving a drawcall, determining a location of primitives in a frame based on the drawcall, dividing the frame into a plurality of tiles, and rendering the tiles, wherein the rendering includes determining a rendering order of the tiles based on primitives included in the tiles, and rendering the tiles according to the rendering order. A graphics processing unit (GPU) is configured to perform the tile-based rendering method, and may include a memory, a processor including at least one core and at least one cache. The GPU may execute a tile-based graphics pipeline for tile-based rendering of images, and allocate tiles including identical primitives to a core.

Abstract: A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.

Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.

Abstract: The present invention relates to an oligonucleotide structure and a method for preparing the same and, more particularly, to an oligonucleotide structure in which a polymer compound is linked to an oligonucleotide via a covalent bond to improve in vivo stability of the oligonucleotide and cellular delivery efficiency of the oligonucleotide; and to a method for preparing the same.

Abstract: A ray tracing method includes determining whether acceleration structure traversal data of a previous ray similar to a received ray is stored in a traversal cache, and reading the stored acceleration structure traversal data, and performing image rendering based on the read acceleration structure traversal data, based on a result of the determining.

Abstract: A method and a graphics processing apparatus for processing texture in a graphics pipeline determine a rendering level of a dynamic texture based on usage information of a target object and render the target object by texturing the target object with the dynamic texture rendered based on the rendering level. The graphics processing apparatus includes at least one cache memory, and at least one processor configured to: perform geometry processing of a dynamic texture to be mapped onto a target object, determine a rendering level of the dynamic texture based on usage information of the target object obtained by the geometry processing of the target object, render the dynamic texture based on the determined rendering level, and render the target object by texturing the target object with the rendered dynamic texture.

Abstract: A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.

Abstract: A method of performing tile-based rendering in a graphics processing apparatus may include: generating a bitstream representing a tile binning result by performing tile binning with initial tiles having initial sizes. A determining as to whether a primitive belonging to an initial tile additionally belongs to other initial tiles bordering the initial tile is made by using the generated bitstream. A determining of a rendering tile is made, in which the rendering tile has a dynamic size and is formed by at least one of the initial tiles that the primitive belongs to, based on a result of the determining of whether the primitive additionally belongs to the other initial tiles. Rendering is performed on the primitive included in the determined rendering tile by using the determined rendering tile.

Abstract: A tile-based rendering method includes receiving a drawcall, determining a location of primitives in a frame based on the drawcall, dividing the frame into a plurality of tiles, and rendering the tiles, wherein the rendering includes determining a rendering order of the tiles based on primitives included in the tiles, and rendering the tiles according to the rendering order. A graphics processing unit (GPU) is configured to perform the tile-based rendering method, and may include a memory, a processor including at least one core and at least one cache. The GPU may execute a tile-based graphics pipeline for tile-based rendering of images, and allocate tiles including identical primitives to a core.

Abstract: A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information.

Abstract: A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM.

Abstract: A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.

Abstract: Provided is a method and apparatus for ray tracing. A traversal unit to process an input ray to be input among a plurality of traversal units may be determined based on age of each of the plurality of traversal units. Age of the determined traversal unit may be determined based on age of each of rays that are processed by the traversal unit.

Abstract: A method of processing ray data the method including receiving ray data stored in input buffers; updating a property of the ray data based on a result of intersection traversal of the ray data; and outputting the ray data to an output buffer or to a feedback buffer from among the input buffers based on the updated property of the ray data. When there is insufficient space in the output buffer to store the ray data, outputting the ray data to the feedback buffer.

Abstract: An apparatus and a method of using an acceleration structure in ray tracing, and a method of ray tracing are provided. The method involves setting a bit stack value of a level of an acceleration structure, moving to a child node among the ray-crossing child nodes and setting a route value of a corresponding level of the acceleration structure, and determining a pop level based on one or more bit stack values.

Abstract: A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.