Abstract: An equalizer includes a delay circuit configured to generate at least one delay signal based on at least one input signal, an encoding circuit configured to generate a plurality of driving signals and a connection switching signal, based on the input signal and the delay signal, a pre-driver configured to generate a plurality of driving switching signals based on the plurality of driving signals, a first differential circuit configured to generate a first differential output signal based on the plurality of driving switching signals, a second differential circuit configured to generate a second differential output signal based on the plurality of driving switching signals, and a connection circuit configured to adjust a connection between the first differential circuit and the second differential circuit based on the connection switching signal.

Abstract: A method includes collecting a first set of images of a scene with a sensor in accordance with a first condition; collecting a second set of images of the scene with the sensor in accordance with a second condition; collecting one or more noise sample sets based on the first set of images and the second set of images; generating a calibrated noise model based on the one or more noise sample sets; and generating a noisy image by applying the calibrated noise model to a noise free image.

Abstract: An analog-to-digital converter (ADC) using a plurality of capacitor digital-to-analog converters (CDACs) includes a plurality of comparators, a plurality of CDACs each configured to generate a reference voltage, and a switch circuit configured to connect one CDAC among the plurality of CDACs to an n+1 comparator, based on a digital value output from an n comparator among the plurality of comparators, and the n+1 comparator may output a digital value based on a result of comparing the reference voltage of one CDAC among the plurality of CDACs with an input voltage.

Abstract: A pulse-amplitude modulation (PAM) transmitter includes a transceiver, and at least one processor connected to the transceiver and configured to identify, from among symbols included in an input signal, a symbol that exceeds a specified transition level, when the symbol exceeding the transition level is identified, obtain a frame buffer including at least one bit among bits constituting the identified symbol, encode input data by inverting at least one bit among the bits constituting the identified symbol, and transmit the frame buffer and the encoded input data.

Abstract: According to an aspect, a data inversion circuit configured to perform DBI-DC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal and a data transmission unit comprising, an auxiliary signal generation unit configured to generate an auxiliary signal that determines whether to perform encoding on the input data by analyzing a plurality of data symbols included in the input data, a channel comprising a plurality of data lines and a data encoding unit configured to generate encoded data by performing DBI (data bus inversion) encoding on the data based on the auxiliary signal and to transmit the generated encoded data to a data reception unit via the channel.

Abstract: A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals.

Abstract: According to an aspect, a data inversion circuit configured to perform DBI-AC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal, a channel comprising N data lines, a first auxiliary signal generation unit configured to generate a first auxiliary signal that determines whether to perform a first encoding on the input data based on the number of each of a plurality of data symbols included in the input data, a first data encoding unit configured to generate intermediate data by performing the first encoding on the input data based on the first auxiliary signal, a second auxiliary signal generation unit configured to generate a second auxiliary signal that determines whether to perform a third encoding on the intermediate data by analyzing the relationship between a plurality of data symbols at a current time point and a plurality of data symbols at a previous time point included in the intermediate data and a second data encoding unit c

Abstract: A high-speed amplifier circuit may include a first bias conversion circuit configured to perform a level-down operation on an input positive differential signal, a second bias conversion circuit configured to perform a level-up operation on an input negative differential signal, a first transmission circuit electrically connected to the first bias conversion circuit and configured to output a first differential signal having a voltage of a level within a first range among all levels, based on the positive differential signal on which the level-down operation has been performed, and a second transmission circuit electrically connected to the second bias conversion circuit and configured to output a second differential signal having a voltage of a level within a second range among all the levels, based on the negative differential signal on which the level-up operation has been performed.

Abstract: A high-speed 4:1 multiplexer according to an embodiment comprises an input circuit unit including a first circuit that receives a first data as an input signal, and outputs a first output data as an output signal, a second circuit that receives a second data as an input signal, and outputs a second output data as an output signal, a third circuit that receives a third data as an input signal, and outputs a third output data as an output signal, and a fourth circuit that receives a fourth data as an input signal, and outputs a fourth output data as an output signal, a first stage for dividing the output data of the input circuit unit by two and receiving as an input signal, and outputting a first intermediate data and a second intermediate data as an output signal and a second stage of receiving the first intermediate data and the second intermediate data as an input signal and outputting a final data as an output signal.

Abstract: The disclosure relates to a pulse amplitude modulation (PAM) data encoding technique capable of reducing effects due to supply noise. A data transmission method according to an embodiment includes identifying an encoding rule of mapping a plurality of pieces of N-bit data and M data symbols, according to a designated level, obtaining a plurality of segmented pieces of data by performing segmentation on input data in units of N bits, mapping the obtained plurality of segmented pieces of data to the M data symbols based on the identified encoding rule, and transmitting the M data symbols obtained as a result of mapping through a plurality of single-ended data lines, wherein an absolute value of a sum of the M data symbols has a value equal to or less than the designated level.

Abstract: A parallel-to-serial converter includes first to fourth input nodes configured to receive first to fourth data input signals, respectively, and an output node configured to output a data output signal. First to fourth logic circuits are provided, which are configured to electrically couple respective ones of the first to fourth input nodes one-at-a-time to the output node, in synchronization with first to fourth clock signals. The first logic circuit includes a first input circuit, a second input circuit, and an output circuit electrically coupled to the first and second input circuits. The output circuit includes a first pull-up transistor and a first pull-down transistor having drain terminals coupled to the output node, a second pull-up transistor connected between a source terminal of the first pull-up transistor and a first power supply node, and a second pull-down transistor connected between a source terminal of the first pull-down transistor and a second power supply node.

Abstract: A pulse-amplitude modulation (PAM) transmitter includes a transceiver, and at least one processor connected to the transceiver and configured to identify, from among symbols included in an input signal, a symbol that exceeds a specified transition level, when the symbol exceeding the transition level is identified, obtain a frame buffer including at least one bit among bits constituting the identified symbol, encode input data by inverting at least one bit among the bits constituting the identified symbol, and transmit the frame buffer and the encoded input data.

Abstract: A high-speed 4:1 multiplexer according to an embodiment comprises an input circuit unit including a first circuit that receives a first data as an input signal, and outputs a first output data as an output signal, a second circuit that receives a second data as an input signal, and outputs a second output data as an output signal, a third circuit that receives a third data as an input signal, and outputs a third output data as an output signal, and a fourth circuit that receives a fourth data as an input signal, and outputs a fourth output data as an output signal, a first stage for dividing the output data of the input circuit unit by two and receiving as an input signal, and outputting a first intermediate data and a second intermediate data as an output signal and a second stage of receiving the first intermediate data and the second intermediate data as an input signal and outputting a final data as an output signal.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Abstract: According to an aspect, a data inversion circuit configured to perform DBI-DC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal and a data transmission unit comprising, an auxiliary signal generation unit configured to generate an auxiliary signal that determines whether to perform encoding on the input data by analyzing a plurality of data symbols included in the input data, a channel comprising a plurality of data lines and a data encoding unit configured to generate encoded data by performing DBI (data bus inversion) encoding on the data based on the auxiliary signal and to transmit the generated encoded data to a data reception unit via the channel.

Abstract: According to an aspect, a data inversion circuit configured to perform DBI-AC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal, a channel comprising N data lines, a first auxiliary signal generation unit configured to generate a first auxiliary signal that determines whether to perform a first encoding on the input data based on the number of each of a plurality of data symbols included in the input data, a first data encoding unit configured to generate intermediate data by performing the first encoding on the input data based on the first auxiliary signal, a second auxiliary signal generation unit configured to generate a second auxiliary signal that determines whether to perform a third encoding on the intermediate data by analyzing the relationship between a plurality of data symbols at a current time point and a plurality of data symbols at a previous time point included in the intermediate data and a second data encoding unit c

Abstract: Generating a layout of an integrated circuit having a plurality of components may be performed by generating placement information of the plurality of components; generating pin position information for pins of the plurality of components; generating grid information according to the pin position information; and generating routing information between two pins of the plurality of components using the grid information.

Abstract: An ESD protection circuit is disclosed. The ESD protection circuit is coupled between a first node and a second node that is coupled to an input of a functional circuit. A first protection circuit is coupled to the first node. The circuit further includes a first path and a second path. The first path includes a second protection circuit that is coupled to the second node, and is AC coupled to the first node. A second circuit path includes a third protection circuit, a resistor coupled between the third protection circuit and the first node, and a switch having a first terminal coupled to the resistor and the third protection circuit. A shunt circuit includes a transistor having a gate terminal coupled to the second terminal of the switch. The transistor, when activated, shunts current from the second node to ground.

Abstract: An ESD protection circuit is disclosed. The ESD protection circuit is coupled between a first node and a second node that is coupled to an input of a functional circuit. A first protection circuit is coupled to the first node. The circuit further includes a first path and a second path. The first path includes a second protection circuit that is coupled to the second node, and is AC coupled to the first node. A second circuit path includes a third protection circuit, a resistor coupled between the third protection circuit and the first node, and a switch having a first terminal coupled to the resistor and the third protection circuit. A shunt circuit includes a transistor having a gate terminal coupled to the second terminal of the switch. The transistor, when activated, shunts current from the second node to ground.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.