Abstract: A semiconductor device includes a substrate; a device isolation layer defining an active region on the substrate; a gate structure on the active region; a source/drain region having a P-type conductivity on at least one side of the gate structure; and a spacer covering a side surface of the gate structure, wherein the spacer includes a first spacer covering the side surface of the gate structure and having a first thickness, a second spacer covering an external side surface of the first spacer and having a second thickness greater than the first thickness, and a third spacer covering an external side surface of the second spacer and having a third thickness smaller than the first thickness, and wherein a level of lower surfaces of the first and second spacers is higher than a level of a lower surface of the third spacer.