Abstract: A memory device includes; a memory cell array including memory cells, a row decoder selecting a word line in response to a received address, and control logic including a sensing capacitor having a size proportional to a size of a word line capacitor associated with the selected word line. The control logic measures line resistance of the selected word line by precharging the selected word line, performing a charge sharing operation between the selected word line and the sensing capacitor following the precharging of the selected word line, and measuring a voltage of the sensing capacitor following the performing of the charge sharing operation.

Abstract: A storage device for performing a reliability check by using error correction code (ECC) data is provided. The storage device includes a memory controller configured to detect the number of errors of second read data read out by a second read operation, based on ECC data of first read data read by a first read operation of a memory device. The memory controller includes a memory check circuit that includes a counter configured to count states of memory cells, a comparator configured to compare respective count numbers of the states with one another, and a register configured to store the number of errors based on a result of the comparison.

Abstract: A storage device for performing a reliability check by using error correction code (ECC) data is provided. The storage device includes a memory controller configured to detect the number of errors of second read data read out by a second read operation, based on ECC data of first read data read by a first read operation of a memory device. The memory controller includes a memory check circuit that includes a counter configured to count states of memory cells, a comparator configured to compare respective count numbers of the states with one another, and a register configured to store the number of errors based on a result of the comparison.

Abstract: A memory device includes; a memory cell array including memory cells, a row decoder selecting a word line in response to a received address, and control logic including a sensing capacitor having a size proportional to a size of a word line capacitor associated with the selected word line. The control logic measures line resistance of the selected word line by precharging the selected word line, performing a charge sharing operation between the selected word line and the sensing capacitor following the precharging of the selected word line, and measuring a voltage of the sensing capacitor following the performing of the charge sharing operation.