Patents by Inventor Jae Gwon Jang
Jae Gwon Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11715645Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: GrantFiled: March 28, 2022Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
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Publication number: 20230068587Abstract: A semiconductor package including a passivation film, a mold layer on the passivation film, a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer, a solder ball on the first portion of the connecting pad, an element on the second portion of the connecting pad, a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer, and a semiconductor chip on the wiring structure may be provided.Type: ApplicationFiled: June 29, 2022Publication date: March 2, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Yae Jung YOON, Eung Kyu KIM, Min Jun BAE, Kyoung Lim SUK, Seok Hyun LEE, Jae Gwon JANG
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Publication number: 20220352050Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Dong Kyu KIM, Jung-Ho PARK, Jong Youn KIM, Yeon Ho JANG, Jae Gwon JANG
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Publication number: 20220262696Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: ApplicationFiled: May 3, 2022Publication date: August 18, 2022Inventors: Jung-Ho PARK, Jin-Woo PARK, Jae Gwon JANG, Gwang Jae JEON
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Patent number: 11404346Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: GrantFiled: January 15, 2020Date of Patent: August 2, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Kyu Kim, Jung-Ho Park, Jong Youn Kim, Yeon Ho Jang, Jae Gwon Jang
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Publication number: 20220216068Abstract: A method for fabricating a semiconductor package, the method including: forming a. release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: ApplicationFiled: March 28, 2022Publication date: July 7, 2022Inventors: Jung-Ho PARK, Jin-Woo PARK, Seok Hyun LEE, Jae Gwon JANG, Gwang Jae JEON
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Patent number: 11328970Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: GrantFiled: May 5, 2020Date of Patent: May 10, 2022Inventors: Jung-Ho Park, Jin-Woo Park, Jae Gwon Jang, Gwang Jae Jeon
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Patent number: 11322368Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: GrantFiled: September 29, 2020Date of Patent: May 3, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
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Patent number: 11121064Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.Type: GrantFiled: March 16, 2020Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Ho Park, Da Hye Kim, Jin-Woo Park, Jae Gwon Jang
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Publication number: 20210257223Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.Type: ApplicationFiled: September 29, 2020Publication date: August 19, 2021Inventors: Jung-Ho PARK, Jin-Woo PARK, Seok Hyun LEE, Jae Gwon JANG, Gwang Jae JEON
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Publication number: 20210066149Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.Type: ApplicationFiled: May 5, 2020Publication date: March 4, 2021Inventors: Jung-Ho PARK, Jin-Woo PARK, Jae Gwon JANG, Gwang Jae JEON
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Publication number: 20210057317Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.Type: ApplicationFiled: March 16, 2020Publication date: February 25, 2021Inventors: Jung-Ho PARK, Da Hye KIM, Jin-Woo PARK, Jae Gwon JANG
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Patent number: 10923650Abstract: In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.Type: GrantFiled: September 4, 2018Date of Patent: February 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-gwon Jang, Baik-woo Lee, Young-jae Kim
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Publication number: 20200411405Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.Type: ApplicationFiled: January 15, 2020Publication date: December 31, 2020Inventors: Dong Kyu KIM, Jung-Ho PARK, Jong Youn KIM, Yeon Ho JANG, Jae Gwon JANG
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Publication number: 20180375017Abstract: In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.Type: ApplicationFiled: September 4, 2018Publication date: December 27, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-gwon JANG, Baik-woo LEE, Young-jae KIM
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Patent number: 10074799Abstract: In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.Type: GrantFiled: April 27, 2016Date of Patent: September 11, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-gwon Jang, Baik-woo Lee, Young-jae Kim
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Patent number: 9893020Abstract: In one embodiment, a semiconductor device comprising, a substrate comprising a wiring layer, a first conductive shielding layer disposed on the substrate and electrically isolated from the wiring layer, the first conductive shielding layer comprising a first bonding surface and a first end surface extending from the first bonding surface, a semiconductor chip disposed on the first conductive shielding layer, a molding member disposed over the first conductive shielding layer to cover the semiconductor chip, a second conductive shielding layer disposed over the first conductive shielding layer and the molding member, the second conductive shielding layer comprising a second bonding surface and a second end surface extending from the second bonding surface, and a bonding portion disposed between the first and second bonding surfaces, the bonding portion comprising a top surface and a bottom surface opposite to the top surface.Type: GrantFiled: August 3, 2016Date of Patent: February 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Baik-Woo Lee, Eun-Seok Song, Young-Jae Kim, Jae-Gwon Jang
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Publication number: 20170294407Abstract: A passive element package includes a first substrate, first passive elements disposed on the first substrate, a second substrate disposed on the first passive elements, second passive elements disposed on the second substrate, and a sealant that seals the first passive elements and the second passive elements. The passive element package can reduce the size of a semiconductor module that includes the passive element package.Type: ApplicationFiled: December 1, 2016Publication date: October 12, 2017Inventors: YOUNG-JAE KIM, BAIK-WOO LEE, TAE-WOO KANG, JAE-GWON JANG
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Patent number: 9627327Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.Type: GrantFiled: July 31, 2015Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Baik-woo Lee, Dong-hun Lee, Jae-gwon Jang, Chul-yong Jang
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Publication number: 20170069828Abstract: In one embodiment, a semiconductor device comprising, a substrate comprising a wiring layer, a first conductive shielding layer disposed on the substrate and electrically isolated from the wiring layer, the first conductive shielding layer comprising a first bonding surface and a first end surface extending from the first bonding surface, a semiconductor chip disposed on the first conductive shielding layer, a molding member disposed over the first conductive shielding layer to cover the semiconductor chip, a second conductive shielding layer disposed over the first conductive shielding layer and the molding member, the second conductive shielding layer comprising a second bonding surface and a second end surface extending from the second bonding surface, and a bonding portion disposed between the first and second bonding surfaces, the bonding portion comprising a top surface and a bottom surface opposite to the top surface.Type: ApplicationFiled: August 3, 2016Publication date: March 9, 2017Inventors: Baik-Woo LEE, Eun-Seok SONG, Young-Jae KIM, Jae-Gwon JANG