Patents by Inventor Jae-Han Park

Jae-Han Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963364
    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok Han Park, Yong Seok Kim, Hui-Jung Kim, Satoru Yamada, Kyung Hwan Lee, Jae Ho Hong, Yoo Sang Hwang
  • Patent number: 11948808
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 2, 2024
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Dong Jin Kim, Jin Han Kim, Won Chul Do, Jae Hun Bae, Won Myoung Ki, Dong Hoon Han, Do Hyung Kim, Ji Hun Lee, Jun Hwan Park, Seung Nam Son, Hyun Cho, Curtis Zwenger
  • Publication number: 20240105963
    Abstract: A method for manufacturing a gas diffusion layer for a fuel cell wherein carbon nanotubes are impregnated into Korean paper, thereby enhancing electroconductivity, and a gas diffusion layer manufactured thereby. The method for manufacturing a gas diffusion layer for a fuel cell which is to manufacture a gas diffusion layer as a constituent member of a unit cell in a fuel cell, includes a support preparation step of preparing a support with Korean paper; a dispersion preparation step of dispersing a carbon substance in a solvent to form a dispersion, a coating step of coating the support with the dispersion, and a thermal treatment step of thermally treating the dispersion-coated support to fix the carbon substance to the support.
    Type: Application
    Filed: March 6, 2023
    Publication date: March 28, 2024
    Inventors: Seung Tak Noh, Ji Han Lee, In Seok Lee, Jae Man Park, Won Jong Choi, Choong Hee Kim, Seong Hwang Kim, Jong Hoon Lee, Soo Jin Park, Seul Yi Lee
  • Publication number: 20240020043
    Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Inventors: Jae-Han PARK, Hyun-Woo KWACK
  • Patent number: 11792916
    Abstract: A printed circuit board includes an insulating layer; a recess portion disposed on one surface of the insulating layer; and a circuit layer disposed on the one surface of the insulating layer and including a signal pattern and a ground pattern. At least a portion of the ground pattern covers at least a portion of the recess portion.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Han Park, Woo Seok Yang
  • Publication number: 20230317454
    Abstract: The present invention is related to a method for fabricating a semiconductor device capable of forming fine patterns. The method for fabricating the semiconductor device according to the present invention may comprise forming an etch mask layer on an etch target layer; forming a spacer structure in which first spacers and second spacers are alternately disposed and spaced apart from each other on the etch mask layer; forming first spacer lines through selective etching of the first spacers; forming second spacer lines through selective etching of the second spacers; and etching the etch target layer to form a plurality of fine line patterns using the first and second spacer lines.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Inventors: Ji Hoon KIM, Jae Han PARK, Chang Hun LEE
  • Patent number: 11710635
    Abstract: The present invention is related to a method for fabricating a semiconductor device capable of forming fine patterns. The method for fabricating the semiconductor device according to the present invention may comprise forming an etch mask layer on an etch target layer; forming a spacer structure in which first spacers and second spacers are alternately disposed and spaced apart from each other on the etch mask layer; forming first spacer lines through selective etching of the first spacers; forming second spacer lines through selective etching of the second spacers; and etching the etch target layer to form a plurality of fine line patterns using the first and second spacer lines.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 25, 2023
    Assignee: SK hynix Inc.
    Inventors: Ji Hoon Kim, Jae Han Park, Chang Hun Lee
  • Publication number: 20230189452
    Abstract: A printed circuit board includes: a core portion including a cavity in one surface thereof; first and second penetration holes disposed in a bottom surface of the cavity and penetrating through the core portion; an electronic component disposed in the cavity; and an insulating material filling the cavity and each of the first and second penetration holes, wherein a sidewall of the cavity is higher than the electronic component.
    Type: Application
    Filed: May 10, 2022
    Publication date: June 15, 2023
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Woo Seok YANG, Jae Han PARK, Jung Hyun CHO
  • Publication number: 20230095087
    Abstract: A printed circuit board includes an insulating layer; a recess portion disposed on one surface of the insulating layer; and a circuit layer disposed on the one surface of the insulating layer and including a signal pattern and a ground pattern. At least a portion of the ground pattern covers at least a portion of the recess portion.
    Type: Application
    Filed: January 3, 2022
    Publication date: March 30, 2023
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Han PARK, Woo Seok YANG
  • Publication number: 20230044357
    Abstract: An exemplary embodiment of the present disclosure provides a physically unclonable function (PUF) cell capable of exhibiting a stable performance and showing an excellent repeatability while being less affected by environmental factors such as a noise, temperature, and bias voltage. The PUF cell generates an output value by combining a scheme of amplifying a threshold voltage difference and a scheme of amplifying an oscillation frequency difference. In an oscillator that generates oscillation signals of different frequencies, the frequency difference of the oscillation signals is amplified by alternately supplying bias voltages of different magnitudes generated by utilizing the threshold voltage difference to a plurality of stages in the oscillator.
    Type: Application
    Filed: May 4, 2022
    Publication date: February 9, 2023
    Applicant: POSTECH Research and Business Development Foundation
    Inventors: Jae Han PARK, Jae Yoon SIM
  • Patent number: 11566131
    Abstract: Disclosed are a composite resin composition and an article containing the same. The composite resin composition may include semicrystalline polyamide; amorphous polyamide; an acrylonitrile-butadiene-styrene (ABS) resin; a compatibilizer; and a strength-reinforcing agent. The article may exhibit superior rigidity equivalent to or greater than that of conventional long-fiber thermoplastics and remarkably excellent dimensional stability. In addition, the composite resin composition and the molded article including the same may be used in replacement of steel parts so as to reduce the weight by about 30%.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: January 31, 2023
    Assignees: Hyundai Motor Company, Kia Motors Corporation, Hyundai Advanced Materials Co., Ltd.
    Inventors: Sang Sun Park, Han Sol Lee, Kyeong Bae Seo, Min Sik Seo, In Seok Kang, Wan Ki Noh, Jae Han Park, Dong Hyun Kim, Hea Lin Kim, Hyung Joo Lee, Seung Soo Hong, Dong Chang Lee, Hyeung Min Lee
  • Publication number: 20220413736
    Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.
    Type: Application
    Filed: September 6, 2022
    Publication date: December 29, 2022
    Inventors: Jae-Han Park, Hyun-Woo Kwack
  • Patent number: 11474727
    Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 18, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae-Han Park, Hyun-Woo Kwack
  • Publication number: 20220270878
    Abstract: The present invention is related to a method for fabricating a semiconductor device capable of forming fine patterns. The method for fabricating the semiconductor device according to the present invention may comprise forming an etch mask layer on an etch target layer; forming a spacer structure in which first spacers and second spacers are alternately disposed and spaced apart from each other on the etch mask layer; forming first spacer lines through selective etching of the first spacers; forming second spacer lines through selective etching of the second spacers; and etching the etch target layer to form a plurality of fine line patterns using the first and second spacer lines.
    Type: Application
    Filed: August 27, 2021
    Publication date: August 25, 2022
    Inventors: Ji Hoon KIM, Jae Han PARK, Chang Hun LEE
  • Patent number: 11422738
    Abstract: A data storage device includes a storage, a buffer memory, and a controller. The controller is configured to control at least one of an input of data to and an output of data from the storage in response to a request transmitted from a host device. The controller is also configured to receive write data transmitted from the host device and cached in the buffer memory, encrypt the write data, and store the encrypted write data in the storage. The controller is further configured to receive read data read from the storage and cached in the buffer memory, decrypt the read data, and provide the decrypted read data to the host device.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyung Min Kim, Do Hun Kim, Jae Han Park
  • Publication number: 20220206701
    Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 30, 2022
    Inventors: Jae-Han PARK, Hyun-Woo KWACK
  • Patent number: 11301158
    Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae-Han Park, Hyun-Woo Kwack
  • Publication number: 20220106447
    Abstract: Disclosed herein are a long glass fiber reinforced thermoplastic resin composition and a molded article including the same. Specifically, the thermoplastic resin composition may include 30% to 70% by weight of polyamide, 20% to 60% by weight of a reinforcing agent which contains a glass fiber and has a flat-plate shape, and 1% to 5% by weight of a silane-based coupling agent.
    Type: Application
    Filed: May 26, 2021
    Publication date: April 7, 2022
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, GS Caltex Corporation
    Inventors: Kyeong Bae Seo, Wan Ki Noh, In Seok Kang, Min Sik Seo, Han Sol Lee, Sang Sun Park, Jae han Park, Hyung Tak Lee, Seok Jin Yong
  • Patent number: 11264114
    Abstract: A test pattern generator includes a random command address generator suitable for generating N combinations, each combination of a command and an address, where N is an integer greater than or equal to 2; an address converter suitable for converting the N combinations into an N-dimensional address; a history storage circuit which is accessed based on the N-dimensional address; and a controller suitable for classifying the N combinations as issue targets, when an area in the history storage circuit, which is accessed based on the N-dimensional address, indicates a value of no hit.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong-Ho Kang, Jae-Han Park
  • Publication number: 20220025177
    Abstract: Disclosed are a composite resin composition and an article containing the same. The composite resin composition may include semicrystalline polyamide; amorphous polyamide; an acrylonitrile-butadiene-styrene (ABS) resin; a compatibilizer; and a strength-reinforcing agent. The article may exhibit superior rigidity equivalent to or greater than that of conventional long-fiber thermoplastics and remarkably excellent dimensional stability. In addition, the composite resin composition and the molded article including the same may be used in replacement of steel parts so as to reduce the weight by about 30%.
    Type: Application
    Filed: November 24, 2020
    Publication date: January 27, 2022
    Inventors: Sang Sun Park, Han Sol Lee, Kyeong Bae Seo, Min Sik Seo, In Seok Kang, Wan Ki Noh, Jae Han Park, Dong Hyun Kim, Hea Lin Kim, Hyung Joo Lee, Seung Soo Hong, Dong Chang Lee, Hyeung Min Lee