Patents by Inventor Jae Heon Kim
Jae Heon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250078136Abstract: Proposed is a method for product recommendation by a server. The method may include receiving a gift recommendation request from a first user terminal for a second user, checking available basic information of the second user, and determining a first recommendation information based on the basic information, wherein the first recommendation information comprises a first recommendation reason and at least one product related to the first recommendation reason. The method may also include determining a second recommendation information not based on the basic information, wherein the second recommendation information comprises a second recommendation reason and at least one product related to the second recommendation reason. The method may further include providing recommendation information comprising the first and second recommendation information to the first user terminal. The first recommendation information may be prioritized for display over the second recommendation information.Type: ApplicationFiled: August 19, 2024Publication date: March 6, 2025Inventors: Ji Hye PARK, Min Seok KIM, Min A KIM, Won Jun JANG, Do Eun KIM, Kyu Min CHOI, Andrew Ho Jun YANG, Eun Soo KIM, Young Woo CHOI, Lim Ah LEE, Hye Jin KIM, Hye Young KANG, Soo Yeon NA, Hyo Eun LEE, Min Seong KIM, Jae Heon KIM, Min Jeong KIM
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Patent number: 11919999Abstract: Provided are a method for preparing a polyetherketoneketone and a polyetherketoneketone prepared thereby, wherein, at the time of a polymerization reaction, nitrogen gas is blown into a liquid reaction medium while stirring, thereby quickly removing hydrochloric acid, which is a by-product generated during the reaction, and preventing aggregation of resin particles, thus suppressing the generation of scales.Type: GrantFiled: November 16, 2018Date of Patent: March 5, 2024Assignee: HANWHA CHEMICAL CORPORATIONInventors: Kwang Seok Jeong, Min Sung Kim, Jae Heon Kim, Ju Young Park, Cho Hee Ahn, Byeong Hyeon Lee, Sang Hyun Cho
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Publication number: 20220257916Abstract: The microneedle assembly of the present invention includes: a main body (110) opened at one side thereof and including a solution reservoir (111) formed in the opened side thereof; a dispensing unit (120) disposed at the other side of the main body (110) in such a manner as to fluidically communicate with the solution reservoir (111); a needle supports (130) positioned at a front portion of each of the dispensing units (120), and protrudingly formed at the other end of the main body (110); a microneedles (140) engaged with the front end of the needle support (130); and a first solution release flow channel (150) formed to penetrate through a portion extending outwardly from a front end of the dispensing unit (120) to the front end of the needle support (130).Type: ApplicationFiled: February 16, 2022Publication date: August 18, 2022Applicant: GL COMPANY Co., Ltd.Inventors: Seong Ok KIM, Young Sook YOUN, Jae Heon KIM
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Publication number: 20200339750Abstract: Provided are a method for preparing a polyetherketoneketone and a polyetherketoneketone prepared thereby, wherein, at the time of a polymerization reaction, nitrogen gas is blown into a liquid reaction medium while stirring, thereby quickly removing hydrochloric acid, which is a by-product generated during the reaction, and preventing aggregation of resin particles, thus suppressing the generation of scales.Type: ApplicationFiled: November 16, 2018Publication date: October 29, 2020Applicant: HANWHA CHEMICAL CORPORATIONInventors: Kwang Seok JEONG, Min Sung KIM, Jae Heon KIM, Ju Young PARK, Cho Hee AHN, Byeong Hyeon LEE, Sang Hyun CHO
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Patent number: 10777742Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.Type: GrantFiled: November 25, 2019Date of Patent: September 15, 2020Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
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Publication number: 20200098984Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
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Publication number: 20200009361Abstract: A micro needle includes: a first base; a second base formed integrally with the top surface of the first base; a needle support formed integrally with the top surface of the second base and leading to a tapered groove penetrating the bottom surface of the first base; and a needle body formed integrally with the center of the top surface of the needle support and having a needle hole leading to the tapered groove. The micro needle allows for low-cost mass production because of the simple structure, and involves applying various drugs by injecting drugs after puncturing the skin.Type: ApplicationFiled: August 30, 2018Publication date: January 9, 2020Applicant: GL.companyInventors: Seong Ok KIM, Yong Sook YOUN, So Min KIM, Jae Heon KIM
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Patent number: 10490741Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.Type: GrantFiled: November 16, 2016Date of Patent: November 26, 2019Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
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Patent number: 10305030Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: GrantFiled: January 8, 2018Date of Patent: May 28, 2019Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
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Publication number: 20180130945Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: ApplicationFiled: January 8, 2018Publication date: May 10, 2018Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
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Patent number: 9865806Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: GrantFiled: November 17, 2016Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
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Publication number: 20170352805Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Inventors: Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim
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Patent number: 9786840Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.Type: GrantFiled: February 13, 2015Date of Patent: October 10, 2017Assignee: SK hynix Inc.Inventors: Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim
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Patent number: 9748472Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.Type: GrantFiled: February 13, 2015Date of Patent: August 29, 2017Assignee: SK hynix Inc.Inventors: Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim
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Patent number: 9722602Abstract: A transmitter includes: a main pull-up driver suitable for pull-up driving an output node; and an auxiliary pull-up driver suitable for pull-up driving the output node based on a voltage of the output node, wherein the auxiliary pull-up driver compensates for non-linear driving current characteristics of the main pull-up driver.Type: GrantFiled: December 22, 2015Date of Patent: August 1, 2017Assignee: SK Hynix Inc.Inventor: Jae-Heon Kim
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Patent number: 9722579Abstract: A semiconductor device may include: a pre-driving unit suitable for transmitting input data to a first node in response to a first control signal; a main driving unit suitable for outputting the input data transmitted to the first node, using a first voltage as a driving voltage; and a bias control unit suitable for supplying a second voltage to the first node in response to a second control signal, the second voltage having a different level from the first voltage.Type: GrantFiled: January 7, 2016Date of Patent: August 1, 2017Assignee: SK Hynix Inc.Inventor: Jae-Heon Kim
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Patent number: 9722580Abstract: A process information extractor circuit includes: a transistor array including a plurality of transistors, and configured such that, among the plurality of transistors, the number of transistors electrically coupled in series is adjusted depending on a code; a current source suitable for adjusting the amount of current flowing through the transistor array to a predetermined value; a comparator suitable for comparing a gate voltage of the transistors electrically coupled in series in the transistor array, with a reference voltage; and a code generator suitable for generating the code according to a comparison result of the comparator.Type: GrantFiled: July 12, 2016Date of Patent: August 1, 2017Assignee: SK Hynix Inc.Inventor: Jae-Heon Kim
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Publication number: 20170201238Abstract: A semiconductor device may include: a pre-driving unit suitable for transmitting input data to a first node in response to a first control signal; a main driving unit suitable for outputting the input data transmitted to the first node, using a first voltage as a driving voltage; and a bias control unit suitable for supplying a second voltage to the first node in response to a second control signal, the second voltage having a different level from the first voltage.Type: ApplicationFiled: January 7, 2016Publication date: July 13, 2017Inventor: Jae-Heon Kim
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Publication number: 20170179951Abstract: A transmitter includes: a main pull-up driver suitable for pull-up driving an output node; and an auxiliary pull-up driver suitable for pull-up driving the output node based on a voltage of the output node, wherein the auxiliary pull-up driver compensates for non-linear driving current characteristics of the main pull-up driver.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventor: Jae-Heon Kim
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Publication number: 20170069837Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: ApplicationFiled: November 17, 2016Publication date: March 9, 2017Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim