Patents by Inventor Jae-ho Ahn

Jae-ho Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865613
    Abstract: There is provided a semiconductor device having an arrangement structure in which high-density line patterns having relatively small widths and relatively tight pitches may be formed. The semiconductor device includes a plurality of line patterns that are spaced apart from one another. The plurality of line patterns include a plurality of main lines that have a first gap therebetween and extend in a first direction and a plurality of sublines that are bent from one end of each of the plurality of main lines. The plurality of sublines have therebetween a distance that is greater than the first gap, and may be spaced apart from extension lines that extend from the one end of each of the plurality of main lines corresponding to the plurality of sublines in the first direction.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-min Lee, Ho-jun Seong, Jae-ho Ahn
  • Patent number: 9646983
    Abstract: A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 9, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-gn Yun, Joon Sung Lim, Jae-ho Ahn
  • Publication number: 20160300791
    Abstract: There is provided a semiconductor device having an arrangement structure in which high-density line patterns having relatively small widths and relatively tight pitches may be formed. The semiconductor device includes a plurality of line patterns that are spaced apart from one another. The plurality of line patterns include a plurality of main lines that have a first gap therebetween and extend in a first direction and a plurality of sublines that are bent from one end of each of the plurality of main lines. The plurality of sublines have therebetween a distance that is greater than the first gap, and may be spaced apart from extension lines that extend from the one end of each of the plurality of main lines corresponding to the plurality of sublines in the first direction.
    Type: Application
    Filed: March 2, 2016
    Publication date: October 13, 2016
    Inventors: Jong-min LEE, Ho-jun SEONG, Jae-ho AHN
  • Publication number: 20160181101
    Abstract: A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 23, 2016
    Inventors: Jang-gn Yun, Joon Sung Lim, Jae-ho Ahn