Abstract: A dual chirp modulation technique is presented for use in telecommunications. The technique includes: generating a first chirp signal ramping at a first rate; generating a second chirp signal ramping at a second rate which differs from the first rate; combining the first chirp signal with the second chirp signal to form a dual chirped signal; and transmitting, the dual chirped signal from a transmitter to a receiver. At least one first chirp signal, the second chirp signal or the dual chirped signal is preferably modulated. At the receiver, the dual chirped signal is correlated with a local chirp signal to help reject out-of-band interferers.

Abstract: An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 ?W with a sensitivity of ?72 dBm at a BER of 10?3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

Abstract: An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 ?W with a sensitivity of ?72 dBm at a BER of 10?3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.