Abstract: A ZQ calibration circuit included in a semiconductor memory device includes a reference voltage selector configured to output a reference voltage selected from among a first reference voltage and a second reference voltage generated based on a first supply voltage and a second supply voltage, in response to a selection signal, a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage, and a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is toggled. Levels of the first and second reference voltages are different from each other, smaller than a level of the first supply voltage, and greater than a level of the second supply voltage.

Abstract: Provided is a transmitting device for enlarging the size of a data eye of a transmission signal. The transmitting device includes an output driver including a plurality of driver circuits that drive a plurality of multi-level signals onto an output node, and a logic circuit configured to detect a direction of a pull-up or pull-down operation of each of the plurality of driver circuits by transitions of the plurality of driver control signals and generate pulse signals. The plurality of multi-level signals are driven based on a plurality of driver control signals and pulse signals, respectively, and the logic circuit provides a pulse signal to at least one static driver circuit connected to a driver control signal that does not transition, from among the plurality of driver circuits.

Abstract: In a transmitter circuit, an impedance calibration circuit is configured to generate an impedance code for impedance matching, an encoder is configured to receive the impedance code and to generate a delay compensation signal based on the impedance code. A delay circuit is configured to output delay data that are delayed from input data by a delay value determined based on the delay compensation signal. A feed-forward equalizer is configured to receive the input data and the delay data, and to equalize the input data based on a main coefficient used for the input data and an equalization coefficient used for the delay data to generate transmission data.

Abstract: Provided is a memory system including: a memory device; and a memory controller configured to transmit a command and address (CA) signal and a data clock (WCK) signal to the memory device, and transmitting a data (DQ) signal to the memory device or receive the DQ signal from the memory device. The memory device may include a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal, a CA sampler configured to sample the CA signal based on the first division clock signal, and a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and the memory controller may include processing circuitry configured to enter CA training in response to receiving the parity error signal.

Abstract: A calibration circuit includes a first, second and third pull-up units each connected to a first power supply node, and first and second pull-down units each connected to a second power supply node. A first code generator is configured to generate a first code by comparing a voltage of a pad at which the first pull-up unit is connected to an external resistor with a reference voltage, and a second code generator is configured to generate a second code by comparing a voltage of a first intermediate node with the reference voltage and output the second code to the first and second pull-down units. A third code generator is configured to generate a third code by comparing a voltage of a second intermediate node between the second pull-down unit and the third pull-up unit with the reference voltage.

Abstract: A multiplexer selects one of a first to a fourth data signal in response to a first to a fourth pulse. The first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse and outputs a first gate signal and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.