Patents by Inventor Jae Hyun Jeon
Jae Hyun Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974469Abstract: Disclosed is a display device and a method of manufacturing the same having improved reliability. In the display device, at least one of a plurality of dielectric films disposed between an oxide semiconductor layer and a light-emitting device includes a lower region disposed on the oxide semiconductor layer and an upper region disposed on the lower region, the upper region including a trap element configured to trap hydrogen, whereby reliability of a thin film transistor including the oxide semiconductor layer is improved.Type: GrantFiled: August 25, 2021Date of Patent: April 30, 2024Assignee: LG Display Co., Ltd.Inventors: Jae Hyun Kim, Jin Chae Jeon, Sun Young Choi, Mi Jin Jeong, Jeoung In Lee
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Publication number: 20240128484Abstract: A fuel cell system and a method of controlling the system are provided. The fuel cell system includes: a fuel cell having a plurality of cells to generate power through a reaction between hydrogen supplied to an anode space and oxygen supplied to a cathode space; a power storage device to be charged with power generated by the fuel cell or discharged to supply power; and a controller. The controller recirculates hydrogen, diffused from the anode space to the cathode space, into the anode space by supplying power charged in the power storage device to the fuel cell when the power generation of the fuel cell is stopped. The controller is configured to control whether to supply the power to the fuel cell based on a pressure measured in the anode space and voltages of the cells that constitute the fuel cell.Type: ApplicationFiled: April 18, 2023Publication date: April 18, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Ji Hoon Ryu, Jae Sung Ryu, Jong Hyun Lee, Yei Sik Jeon, Young Wook Cheong
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Patent number: 11949885Abstract: An intra prediction method and a device using the intra prediction method are provided. The intra prediction method includes the steps of: deriving a current prediction mode as a prediction mode of a current block; constructing neighboring samples of the current block with available reference samples; filtering the available reference samples; and generating predicted samples of the current block on the basis of the filtered available reference samples. The filtering step includes performing the filtering using the available reference sample located in the prediction direction of the current prediction mode and a predetermined number of available reference samples neighboring to the prediction direction of the current prediction mode.Type: GrantFiled: May 2, 2023Date of Patent: April 2, 2024Assignee: LG ELECTRONICS INC.Inventors: Yong Joon Jeon, Seung Wook Park, Jung Sun Kim, Joon Young Park, Byeong Moon Jeon, Jae Hyun Lim
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Publication number: 20240098382Abstract: An image processing device including: a decision pixel manager for setting a decision area for a defect candidate pixel, and determining a first decision pixel and a second decision pixel, based on first phase information of pixels included in the decision area with respect to a first modulation frequency of a sensing light source among the pixels; a target pixel determiner for calculating a phase difference between the first decision pixel and the second decision pixel, based on second phase information of the pixels with respect to a second modulation frequency of the sensing light source, and determining the defect candidate pixel as a target pixel, corresponding to that the phase difference exceeds a predetermined reference value; and a phase corrector for changing a phase of the target pixel, based on the phase difference.Type: ApplicationFiled: February 28, 2023Publication date: March 21, 2024Applicant: SK hynix Inc.Inventors: Woo Young JEONG, Ja Min KOO, Tae Hyun KIM, Jae Hwan JEON, Chang Hun CHO
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Patent number: 11928070Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.Type: GrantFiled: October 20, 2021Date of Patent: March 12, 2024Assignee: SK hynix Inc.Inventors: Yong Tae Jeon, Byung Cheol Kang, Seung Duk Cho, Sang Hyun Yoon, Se Hyeon Han, Jae Young Jang
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Publication number: 20240066960Abstract: An embodiment vehicle door opening/closing system includes an inner panel defining a door open portion of a vehicle, the inner panel including an installation groove having a protruding or recessed shape, a driving device disposed in the installation groove of the inner panel, and a link mechanism installed on a chassis through a rotating shaft, a first end of the link mechanism being connected to the driving device such that power is transferred thereto, and a second end of the link mechanism being connected to a door such that, during driving of the driving device, the link mechanism rotates with reference to the rotating shaft to open/close the door.Type: ApplicationFiled: January 23, 2023Publication date: February 29, 2024Inventors: Chang Hak Kang, Jae Seung Lee, Gook Hyun Jeon, Chan Woong Jeon, Sang Kyoung Han, Hae Hoon Lee
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Publication number: 20220302458Abstract: Disclosed are a flexible electrode substrate including a porous electrode, a method for manufacturing the flexible electrode substrate, and an energy storage element including the flexible electrode substrate. The flexible electrode substrate can be attached to various objects due to the excellent electrochemical properties and the adhesive properties thereof and thus is very useful. In particular, since the flexible electrode substrate can be used as an electrode of an energy storage element, an energy storage element including the flexible electrode substrate can be attached to various objects and thus can be used as a sticker-type energy storage element. In addition, the flexible electrode substrate can be easily manufactured by transfer method using a difference in adhesive strength and thus allows a simple manufacturing process thereof. Furthermore, electrodes having various patterns can be manufactured with high level of efficiency through simple adjustment of the manufacturing process.Type: ApplicationFiled: August 13, 2019Publication date: September 22, 2022Applicant: KOREA INSTITUTE OF ENERGY RESEARCHInventors: Ha Na YOON, Chung Yul YOO, Sang Hyun PARK, Jung Joon YOO, Young A LEE, Jae Hyun JEON, Kyu Yeon JANG
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Patent number: 9525363Abstract: Disclosed is a method for voltage dip compensation of inverter, the method including reducing an output frequency of an inverter to obtain a regenerative energy when it is determined that power failure has occurred during the inverter operation, adjusting increase/decrease of inverter output frequency in response to size of exceeding current and voltage based on an output current and DC-link voltage of the inverter, increasing the inverter output frequency in order to prevent excessive current flow when power restoration occurs at a power failure state, and returning to a speed prior to the momentary voltage dip by gradually increasing the inverter output frequency in a state where the inverter output frequency does not exceed an over-current limit by monitoring the inverter output frequency.Type: GrantFiled: June 9, 2015Date of Patent: December 20, 2016Assignee: LSIS CO., LTD.Inventor: Jae Hyun Jeon
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Publication number: 20150357936Abstract: Disclosed is a method for voltage dip compensation of inverter, the method including reducing an output frequency of an inverter to obtain a regenerative energy when it is determined that power failure has occurred during the inverter operation, adjusting increase/decrease of inverter output frequency in response to size of exceeding current and voltage based on an output current and DC-link voltage of the inverter, increasing the inverter output frequency in order to prevent excessive current flow when power restoration occurs at a power failure state, and returning to a speed prior to the momentary voltage dip by gradually increasing the inverter output frequency in a state where the inverter output frequency does not exceed an over-current limit by monitoring the inverter output frequency.Type: ApplicationFiled: June 9, 2015Publication date: December 10, 2015Applicant: LSIS CO., LTD.Inventor: Jae Hyun JEON
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Patent number: 9093892Abstract: Provided is an apparatus and method for controlling medium voltage inverter, whereby a frequency outputted by the medium voltage inverter is fixed, in a case an instantaneous power interrupt occurs while the medium voltage inverter drives a motor, and a voltage level of an AC power generated by the medium voltage inverter is reduced and outputted in response to a predetermined deceleration slope to control the medium voltage inverter.Type: GrantFiled: July 17, 2012Date of Patent: July 28, 2015Assignee: LSIS Co., Ltd.Inventor: Jae Hyun Jeon
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Patent number: 8970159Abstract: Provided are a method for compensating instantaneous power failure in medium voltage inverter and a medium voltage inverter system by using the same, the method for compensating instantaneous power failure in medium voltage inverter including a plurality of power cells supplying a phase voltage to a motor by being connected to the motor in series, the method including decreasing an output frequency of the plurality of power cells by as much as a predetermined value at a relevant point where an input voltage of the plurality of power cells is less than a reference value, decreasing the output frequency at a predetermined deceleration gradient, and maintaining the output frequency during restoration of input voltage as long as a predetermined time, in a case the input voltage is restored.Type: GrantFiled: September 14, 2012Date of Patent: March 3, 2015Assignee: LSIS Co., Ltd.Inventors: Jung Muk Choi, Seung Ho Na, Jae Hyun Jeon, Sung Guk Ahn
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Publication number: 20130076285Abstract: Provided are a method for compensating instantaneous power failure in medium voltage inverter and a medium voltage inverter system by using the same, the method for compensating instantaneous power failure in medium voltage inverter including a plurality of power cells supplying a phase voltage to a motor by being connected to the motor in series, the method including decreasing an output frequency of the plurality of power cells by as much as a predetermined value at a relevant point where an input voltage of the plurality of power cells is less than a reference value, decreasing the output frequency at a predetermined deceleration gradient, and maintaining the output frequency during restoration of input voltage as long as a predetermined time, in a case the input voltage is restored.Type: ApplicationFiled: September 14, 2012Publication date: March 28, 2013Applicant: LSIS CO., LTD.Inventors: JUNG MUK CHOI, SEUNG HO NA, JAE HYUN JEON, SUNG GUK AHN
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Patent number: 8361177Abstract: Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 ?m or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.Type: GrantFiled: December 11, 2008Date of Patent: January 29, 2013Assignees: K.C. Tech Co., Ltd., IUCF-HYUInventors: Dae Hyeong Kim, Seok Min Hong, Jae Hyun Jeon, Un Gyu Park, Jea Gun Park, Yong Kuk Kim
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Publication number: 20130020976Abstract: Provided is an apparatus and method for controlling medium voltage inverter, whereby a frequency outputted by the medium voltage inverter is fixed, in a case an instantaneous power interrupt occurs while the medium voltage inverter drives a motor, and a voltage level of an AC power generated by the medium voltage inverter is reduced and outputted in response to a predetermined deceleration slope to control the medium voltage inverter.Type: ApplicationFiled: July 17, 2012Publication date: January 24, 2013Applicant: LSIS CO., LTD.Inventor: Jae Hyun JEON
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Patent number: 8345455Abstract: The present invention relates to a control device and a control method of a high voltage inverter capable of automatically and accurately setting up neutral point information at a master controller and a plurality of cell controllers of the high voltage inverter, wherein a master controller determines information of neutral point set up to itself and performs a communication with the cell controllers each disposed at each of a plurality of U phase unit cells, a plurality of V phase unit cells and a plurality of W phase unit cells to determine the neutral point information preset on the cell controllers and to detect a cell controller set up with neutral point information different from that of the master controller, and to correct the neutral point information of the detected relevant cell controller using the neutral point information set up in the master controller, thereby operating the high voltage inverter.Type: GrantFiled: February 22, 2010Date of Patent: January 1, 2013Assignee: LS Industrial Systems Co., Ltd.Inventor: Jae Hyun Jeon
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Publication number: 20110050199Abstract: The present invention relates to a control device and a control method of a high voltage inverter capable of automatically and accurately setting up neutral point information at a master controller and a plurality of cell controllers of the high voltage inverter, wherein a master controller determines information of neutral point set up to itself and performs a communication with the cell controllers each disposed at each of a plurality of U phase unit cells, a plurality of V phase unit cells and a plurality of W phase unit cells to determine the neutral point information preset on the cell controllers and to detect a cell controller set up with neutral point information different from that of the master controller, and to correct the neutral point information of the detected relevant cell controller using the neutral point information set up in the master controller, thereby operating the high voltage inverter.Type: ApplicationFiled: February 22, 2010Publication date: March 3, 2011Inventor: Jae Hyun JEON
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Publication number: 20090133336Abstract: Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 ?m or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.Type: ApplicationFiled: December 11, 2008Publication date: May 28, 2009Applicants: K.C. TECH CO., LTD., IUCF-HYUInventors: Dae Hyeong Kim, Seok Min Hong, Jae Hyun Jeon, Un Gyu Paik, Jea Gun Park, Yong Kuk Kim
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Publication number: 20090100765Abstract: Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 ?m or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.Type: ApplicationFiled: December 11, 2008Publication date: April 23, 2009Applicants: K.C. TECH CO., LTD., IUCF-HYUInventors: Dae Hyeong Kim, Seok Min Hong, Jae Hyun Jeon, Un Gyu Paik, Jea Gun Park, Yong Kuk Kim
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Patent number: 7470295Abstract: Disclosed herein is a polishing slurry for chemical mechanical polishing. The polishing slurry comprises polishing particles, which have a particle size distribution including separated fine and large polishing particle peaks. The polishing slurry also comprises polishing particles, which have a median size of 50-150 nm. The present invention provides the slurry having an optimum polishing particle size, in which the polishing particle size is controlled and which is useful to produce semiconductors having fine design rules by changing the production conditions of the slurry. The present invention also provides the polishing slurry and a method of producing the same, in which a desirable CMP removal rate is assured and scratches are suppressed by controlling a polishing particle size distribution, and a method of polishing a substrate.Type: GrantFiled: March 11, 2005Date of Patent: December 30, 2008Assignees: K.C. Tech Co., Ltd., IUCF-HYUInventors: Dae Hyung Kim, Seok Min Hong, Jae Hyun Jeon, Ho Seong Kim, Hyun Soo Park, Un Gyu Paik, Jae Gun Park, Yong Kuk Kim
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Patent number: 7364600Abstract: Disclosed herein is a polishing slurry and a method of producing the same. The polishing slurry has high selectivity in terms of a polishing speed of an oxide layer to that of a nitride layer used in CMP of an STI process which is essential to produce ultra highly integrated semiconductors having a design rule of 256 mega D-RAM or more, for example, a design rule of 0.13 ?m or less. A method and a device for pre-treating polishing particles, a dispersing device and a method of operating the dispersing device, a method of adding a chemical additive and an amount added, and a device for transferring samples are properly employed to produce a high performance nano ceria slurry essential to CMP for a process of producing ultra highly integrated semiconductors of 0.13 ?m or less, particularly, the STI process.Type: GrantFiled: May 11, 2005Date of Patent: April 29, 2008Assignees: K.C. Tech Co., Ltd., IUCF-HYUInventors: Dae Hyeong Kim, Seok Min Hong, Jae Hyun Jeon, Ho Seong Kim, Hyun Soo Park, Un Gyu Paik, Jae Gun Park, Yong Kuk Kim