Patents by Inventor Jae-Ick SON
Jae-Ick SON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240163234Abstract: Provided is a method of operating a terminal. The method includes determining a profile item applicable to the profile view for the account based on an input received by the terminal and a coordinate indicating a position where the profile item is provided on the profile view. The method includes displaying the profile item on a screen of the terminal based on the determined profile item and the determined coordinate. The method includes receiving an input related to the profile item, and displaying a visual effect corresponding to the input on the screen.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Inventors: Sul Gi KIM, Ji Hwi PARK, Yun Jin KIM, Nam Hee KO, Hye Seon KIM, Bo Young JANG, Seung Yong JI, Jae Ick HWANG, Sun Je BANG, Ji On CHU, Hye Mi LEE, Shin Young LEE, Seung Uk JEONG, Eun Ho SON, Sang Min SEO, Jeong Ryeol CHOI
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Patent number: 11676836Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensType: GrantFiled: November 29, 2021Date of Patent: June 13, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Ick Son, Dae Seok Byeon, Bong Soon Lim
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Publication number: 20220084859Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensType: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jae Ick SON, Dae Seok BYEON, Bong Soon LIM
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Patent number: 11201069Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensType: GrantFiled: August 17, 2020Date of Patent: December 14, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Ick Son, Dae Seok Byeon, Bong Soon Lim
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Patent number: 11195587Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, an input/output circuit, a sensing line, and a detecting circuit. The first semiconductor chip includes bitlines, wordlines, first bonding pads electrically connected to the bitlines, second bonding pads electrically connected to the wordlines, and memory cells electrically connected to the bitlines and the wordlines. The second semiconductor chip includes third bonding pads that are electrically connected to the first bonding pads and fourth bonding pads that are electrically connected to the second bonding pads. The input/output circuit writes data to the memory cells via the third bonding pads. The sensing line extends along edge portions of at least one of the first and second semiconductor chips. The detecting circuit is in the second semiconductor chip and can detect defects from at least one of the first and second semiconductor chips using the sensing line.Type: GrantFiled: May 28, 2020Date of Patent: December 7, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Ick Son, Dae Seok Byeon, Bong Soon Lim
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Publication number: 20210090922Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensType: ApplicationFiled: August 17, 2020Publication date: March 25, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jae Ick SON, Dae Seok BYEON, Bong Soon LIM
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Publication number: 20210090663Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, an input/output circuit, a sensing line, and a detecting circuit. The first semiconductor chip includes bitlines, wordlines, first bonding pads electrically connected to the bitlines, second bonding pads electrically connected to the wordlines, and memory cells electrically connected to the bitlines and the wordlines. The second semiconductor chip includes third bonding pads that are electrically connected to the first bonding pads and fourth bonding pads that are electrically connected to the second bonding pads. The input/output circuit writes data to the memory cells via the third bonding pads. The sensing line extends along edge portions of at least one of the first and second semiconductor chips. The detecting circuit is in the second semiconductor chip and can detect defects from at least one of the first and second semiconductor chips using the sensing line.Type: ApplicationFiled: May 28, 2020Publication date: March 25, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jae Ick SON, Dae Seok BYEON, Bong Soon LIM
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Patent number: 10140415Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.Type: GrantFiled: January 17, 2017Date of Patent: November 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-eun Lee, Sung-hoon Kim, Jae-ick Son, Hyang-ja Yang
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Patent number: 9929172Abstract: A method of verifying a layout of a vertical memory device includes classifying a plurality of channel holes included in the layout of the vertical memory device into a plurality of types based on at least one of a distance between each channel hole and an isolation region adjacent thereto, shapes of the plurality of channel holes in the layout, and coordinates of the plurality of channel holes in the layout. Types of channel holes connected to each of a plurality of bit lines included in the layout are identified, and a determination is made whether loads of the plurality of bit lines are equalized, based on the identified types of the channel holes for each bit line.Type: GrantFiled: August 31, 2016Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Won Kim, Sung-Hoon Kim, Jae-Ick Son
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Patent number: 9799672Abstract: A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer covering the peripheral circuit, a base layer formed on the lower insulation layer, a memory cell array formed on the base layer, an upper insulation layer covering the memory cell array and a plurality of input-output pads formed on a bottom surface of the semiconductor substrate. At least one of the input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction. The sizes of the memory device and the memory package including the memory device may be reduced through the COP structure and efficient arrangement of the input-output pads.Type: GrantFiled: February 3, 2016Date of Patent: October 24, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Ick Son, Sung-Hoon Kim
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Publication number: 20170255742Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.Type: ApplicationFiled: January 17, 2017Publication date: September 7, 2017Inventors: Jae-eun Lee, Sung-hoon Kim, Jae-ick Son, Hyang-ja Yang
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Publication number: 20170243882Abstract: A method of verifying a layout of a vertical memory device includes classifying a plurality of channel holes included in the layout of the vertical memory device into a plurality of types based on at least one of a distance between each channel hole and an isolation region adjacent thereto, shapes of the plurality of channel holes in the layout, and coordinates of the plurality of channel holes in the layout. Types of channel holes connected to each of a plurality of bit lines included in the layout are identified, and a determination is made whether loads of the plurality of bit lines are equalized, based on the identified types of the channel holes for each bit line.Type: ApplicationFiled: August 31, 2016Publication date: August 24, 2017Inventors: KI-WON KIM, SUNG-HOON KIM, JAE-ICK SON
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Publication number: 20160307910Abstract: A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer covering the peripheral circuit, a base layer formed on the lower insulation layer, a memory cell array formed on the base layer, an upper insulation layer covering the memory cell array and a plurality of input-output pads formed on a bottom surface of the semiconductor substrate. At least one of the input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction. The sizes of the memory device and the memory package including the memory device may be reduced through the COP structure and efficient arrangement of the input-output pads.Type: ApplicationFiled: February 3, 2016Publication date: October 20, 2016Inventors: Jae-Ick SON, Sung-Hoon KIM