Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.

Abstract: A method of verifying a layout of a vertical memory device includes classifying a plurality of channel holes included in the layout of the vertical memory device into a plurality of types based on at least one of a distance between each channel hole and an isolation region adjacent thereto, shapes of the plurality of channel holes in the layout, and coordinates of the plurality of channel holes in the layout. Types of channel holes connected to each of a plurality of bit lines included in the layout are identified, and a determination is made whether loads of the plurality of bit lines are equalized, based on the identified types of the channel holes for each bit line.

Abstract: A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer covering the peripheral circuit, a base layer formed on the lower insulation layer, a memory cell array formed on the base layer, an upper insulation layer covering the memory cell array and a plurality of input-output pads formed on a bottom surface of the semiconductor substrate. At least one of the input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction. The sizes of the memory device and the memory package including the memory device may be reduced through the COP structure and efficient arrangement of the input-output pads.

Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.

Abstract: A method of verifying a layout of a vertical memory device includes classifying a plurality of channel holes included in the layout of the vertical memory device into a plurality of types based on at least one of a distance between each channel hole and an isolation region adjacent thereto, shapes of the plurality of channel holes in the layout, and coordinates of the plurality of channel holes in the layout. Types of channel holes connected to each of a plurality of bit lines included in the layout are identified, and a determination is made whether loads of the plurality of bit lines are equalized, based on the identified types of the channel holes for each bit line.

Abstract: A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer covering the peripheral circuit, a base layer formed on the lower insulation layer, a memory cell array formed on the base layer, an upper insulation layer covering the memory cell array and a plurality of input-output pads formed on a bottom surface of the semiconductor substrate. At least one of the input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction. The sizes of the memory device and the memory package including the memory device may be reduced through the COP structure and efficient arrangement of the input-output pads.